Reverse leakage reduction and vertical height shrinking of diode with halo doping

• US 20090268508A1
• Filed: 04/29/2008
• Published: 10/29/2009
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Clark, Mark H., Kumar, Tanmay, Herner, S. Brad, Chen, Xiying
• Granted Patent: US 8,450,835 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Claims

1. A semiconductor diode device, comprising:

a first conductivity type region;

a second conductivity type region, wherein the second conductivity type is different from the first conductivity type;

an intrinsic region located between the first conductivity type region and the second conductivity type region; and

a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region.

2. A device of claim 1, further comprising a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

3. A device of claim 1, wherein the first halo region is lightly doped, and wherein the first conductivity type region and the second conductivity type region are heavily doped.

4. A device of claim 1, wherein:

doping concentration of the first conductivity type region and doping concentration of second conductivity type region are higher than 1×

10¹⁹ cm<sup>−

3</sup>;

doping concentration of the halo region is higher than 1×

10¹⁷ cm<sup>−

3</sup> and lower than 1×

10¹⁹ cm<sup>−

3</sup>;

the first conductivity type region and the second conductivity type region have a thickness ranging from 5 angstroms to 1 micron; and

the halo region has a thickness ranging from 10 angstroms to 3 microns.

5. A device of claim 1, wherein:

the diode is selected from a group consisting of p⁺-n⁻

-i-n⁺semiconductor diode, p⁺-i-p⁻

-n⁺ semiconductor diode, p⁺-n⁻

-i-p⁻

-n+ semiconductor diode, n⁺-i-nⁿ⁻

-p⁺ semiconductor diode, n+-p⁻

-p⁺ semiconductor diode, and n+-p⁻

-i-n⁻

p⁺ semiconductor diode;

the regions of the diode are arranged vertically in series; and

the diode has a substantially cylindrical shape.

6. A nonvolatile memory device, comprising:

at least one memory cell which comprises a steering element and a storage element, wherein the steering element comprises the diode of claim 1; and

a first electrode and a second electrode electrically contacting the at least one memory cell.

7. A device of claim 6, wherein the memory cell type is selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

8. A device of claim 6, wherein the storage element comprises a resistivity switching element.

9. A device of claim 8, wherein the resistivity switching element comprises a metal oxide antifuse dielectric layer.

10. A device of claim 9, wherein the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes.

11. A device of claim 6, wherein the memory cell is a read/write memory cell or a rewritable memory cell.

12. A device of claim 6, wherein the nonvolatile memory device comprises a monolithic, three dimensional array of memory cells.

13. A method of making a nonvolatile memory device, comprising:

forming a first conductivity type region;

forming a second conductivity type region, wherein the second conductivity type is different from the first conductivity type;

forming an intrinsic region between the first conductivity type region and the second conductivity type region; and

forming a first halo region of the first conductive type between the second conductivity type region and the intrinsic region.

14. A method of claim 13, further comprising forming a second halo region of the second conductivity type between the first conductivity type region and the intrinsic region.

15. A method of claim 13, wherein the halo region is lightly doped, and wherein the first conductivity type region and the second conductivity type region are heavily doped.

16. A method of claim 13, wherein:

doping concentration of the first conductivity type region and doping concentration of second conductivity type region are higher than 1×

10¹⁹ cm<sup>−

3</sup>;

doping concentration of the halo region is higher than 1×

10¹⁷ cm<sup>−

3</sup> and lower than 1×

10¹⁹ cm<sup>−

3</sup>;

the first conductivity type region and the second conductivity type region have a thickness ranging from 5 angstroms to 1 micron; and

the halo region has a thickness ranging from 10 angstroms to 3 microns.

17. A method of claim 13, wherein:

the diode is selected from a group consisting of p⁺-n⁻

-i-n⁺ semiconductor diode, p³⁰-i-p⁻

-n⁺ semiconductor diode, p⁺-n³¹-i-p-n⁺ semiconductor diode, n⁺-i-n⁻

-p⁺ semiconductor diode, n⁺-p⁻

-i-p⁺ semiconductor diode, and n⁺-p⁻

-i-n⁻

-p⁺ semiconductor diode;

the regions of the diode are arranged vertically in series; and

the diode has a substantially cylindrical shape.

18. A method of claim 13, further comprising:

forming a storage element in contact with the diode; and

forming a first electrode and a second electrode.

19. The method of claim 18, wherein the storage element comprises a metal oxide antifuse dielectric layer.

20. A method of claim 19, wherein the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes.