Network routing apparatus for enhanced efficiency and monitoring capability
First Claim
1. A network device comprising:
- a memory; and
a port controller coupled to the memory, the port controller comprising;
a packet input circuit;
a buffer manager circuit; and
a packet output circuit;
wherein the memory is located external to the port controller;
wherein the packet input circuit is configured to receive incoming data packets received by the network device, and to generate associated header information for each data packet by performing a lookup using information in a packet header of the data packet;
wherein the memory is configured to store the data packets after processing of the incoming data packets by the packet input circuit and to store information enabling lookups to be performed for the data packets;
wherein the buffer manager circuit is configured tocause a lookup to be performed in the memory for each data packet using the information enabling lookups stored in the memory; and
wherein the packet output circuit is configured to receive the data packets stored in the memory and to assemble outgoing data packets from contents of the stored data packets and the associated header information generated for the data packets.
6 Assignments
0 Petitions
Accused Products
Abstract
According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.
-
Citations
54 Claims
-
1. A network device comprising:
-
a memory; and a port controller coupled to the memory, the port controller comprising; a packet input circuit; a buffer manager circuit; and a packet output circuit; wherein the memory is located external to the port controller; wherein the packet input circuit is configured to receive incoming data packets received by the network device, and to generate associated header information for each data packet by performing a lookup using information in a packet header of the data packet; wherein the memory is configured to store the data packets after processing of the incoming data packets by the packet input circuit and to store information enabling lookups to be performed for the data packets; wherein the buffer manager circuit is configured to cause a lookup to be performed in the memory for each data packet using the information enabling lookups stored in the memory; and wherein the packet output circuit is configured to receive the data packets stored in the memory and to assemble outgoing data packets from contents of the stored data packets and the associated header information generated for the data packets. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
-
-
54-57. -57. (canceled)
Specification