SYSTEMS, DEVICES, AND METHODS FOR SEMICONDUCTOR DEVICE TEMPERATURE MANAGEMENT

• US 20090305482A1
• Filed: 06/08/2009
• Published: 12/10/2009
• Est. Priority Date: 06/06/2008
• Status: Active Grant

• Current Assignee: Coolsilicon, LLC
• Original Assignee: Coolsilicon, LLC
• Inventors: Zeyen, Benedikt, Winter, Bradley J.
• Granted Patent: US 7,781,263 B2
• Time in Patent Office: Days
• US Class Current: 438/456
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein.

Claims

1. A method of fabricating an IC die that includes at least one intra-die cooling structure, comprising:

providing a first substrate layer;

defining at least one recessed portion in a first surface of said substrate layer;

providing a second substrate layer;

bonding said first substrate layer to a second surface of said second substrate layer to form at least one intra-layer coolant channel;

removing at least one portion of a second surface of said first substrate layer to form at least one inter-layer coolant channel; and

bonding at least one of a first surface of said second substrate layer or a second surface of said first substrate layer to at least one other layer of said IC die.

2. The method of claim 1, wherein said defining at least one recessed portion in said first surface of said substrate layer includes defining by a subtractive process.

3. The method of claim 2, wherein said defining by a subtractive process includes defining by a process selected from the group consisting of:

physical etching, ion-beam etching, plasma etching, chemical etching, reactive ion etching, vapor phase etching, isotropic wet etching, anisotropic wet etching, photolithographic, reactive ion etch, and wet chemical etch.

4. The method of claim 1, wherein said defining at least one recessed portion in said first surface of said substrate layer includes defining by an additive process.

5. The method of claim 4, wherein said defining by an additive process includes defining by a process selected from the group consisting of:

UV sensitive and UV insensitive deposition and hardening or softening, spray-on deposition, spin-on deposition, immersion coating, sputtering, lithography, chemical vapor deposition, physical vapor deposition, plating, silk-screening, casting, tape casting, plasma spraying, plasma polymerization, plastic spraying, and micromolding.

6. The method of claim 1, further comprising:

depositing at least one sacrificial material in said at least one recessed portion.

7. The method of claim 6, wherein said depositing at least one sacrificial material includes depositing polysilicon.

8. The method of claim 1, further comprising:

depositing at least one protective material in said at least one recessed portion.

9. The method of claim 8, wherein said depositing at least one protective material includes depositing silicon dioxide.

10. A method of fabricating an IC die that includes at least one coolant fluid reservoir, comprising:

providing a first substrate layer that includes a first surface and a second surface;

defining at least one recess in said second surface;

filling said at least one recess with a structural material to form at least one reservoir pillar;

etching said first surface to expose said at least one reservoir pillar at said second surface;

etching at said first surface, at least one region adjacent to said at least one reservoir pillar, to form at least one coolant housing portion; and

bonding at least one of said first surface or said second surface to at least one other layer of said IC die.

11. The method of claim 10, further comprising:

forming, at said second surface, at least one heat sink.

12. The method of claim 11, wherein forming, at said second surface, at least one heat sink includes using a sputtering process.

13. The method of claim 12, wherein said forming at least one heat sink includes sputtering a TI/Au layer stack on said second surface and using a copper electroplating process.

14. The method of claim 10, further comprising:

forming at least one coolant inlet in said coolant reservoir.

15. A method of fabricating an IC die that includes at least one intra-die cooling structure, comprising:

providing at least one semiconductor substrate layer with at least one coolant channel formed therein;

providing at least one coolant reservoir layer that includes at least one coolant channel interface adapted to be fluidically coupled to said at least one coolant channel;

bonding said at least one semiconductor substrate layer to said at least one coolant reservoir layer such that said at least one coolant channel interface is interfaced with said at least one coolant channel.

16. A method of fabricating an IC die that includes at least one intra-die cooling structure, comprising:

providing a first substrate layer that includes a first surface and a second surface;

defining at least one recessed portion in a second surface of said substrate layer;

providing a second substrate layer;

defining at least one recessed portion in a second surface of said substrate layer;

bonding said second surface of said first substrate layer to said first surface of said second substrate layer to form at least one coolant channel between said first substrate layer and said second substrate layer.

17. A method of fabricating an IC die that includes at least one intra-die cooling structure, comprising:

providing a first substrate layer that includes a first surface and a second surface;

defining at least one recessed portion in a second surface of said substrate layer;

disposing at least one sacrificial layer in said at least one recessed portion;

forming at least one sacrificial structure upon the sacrificial layer;

forming at least one support structure at said second surface; and

removing said at least one sacrificial layer and said at least one sacrificial structure to form at least one intra-die cooling channel.