Method of Manufacturing a Resistivity Changing Memory Cell, Resistivity Changing Memory Cell, Integrated Circuit, and Memory Module
First Claim
1. A method of manufacturing an integrated circuit comprising a plurality of resistivity changing memory cells, the method comprising:
- forming a stack of layers comprising a resistivity changing layer, a first conductive layer, a second conductive layer, and a masking layer which are stacked above each other in this order;
patterning the second conductive layer using the masking layer as a patterning mask;
patterning the first conductive layer using the second conductive layer as a patterning mask; and
patterning the resistivity changing layer using the first conductive layer as a patterning mask.
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Abstract
According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask.
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Citations
24 Claims
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1. A method of manufacturing an integrated circuit comprising a plurality of resistivity changing memory cells, the method comprising:
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forming a stack of layers comprising a resistivity changing layer, a first conductive layer, a second conductive layer, and a masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A resistivity changing memory cell, comprising:
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a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order, wherein the first conductive layer and the second conductive layer together form at least one structure selected from the group consisting of a contact of the resistivity changing memory cell, an electrode of the resistivity changing memory cell, and a composite structure comprising a memory cell contact and a memory cell electrode, and wherein a ratio between a thickness of the first conductive layer and a thickness of the second conductive layer ranges between about 15 and about 30. - View Dependent Claims (21)
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22. An integrated circuit comprising a resistivity changing memory cell, the resistivity changing memory cell comprising a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order,
wherein the first conductive layer and the second conductive layer together form at least one structure selected from a group of structures consisting of a contact of the memory cell, an electrode of the memory cell, or a composite structure comprising a memory cell contact and a memory cell electrode, and wherein a ratio between a thickness of the first conductive layer and a thickness of the second conductive layer ranges between about 15 and about 30.
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23. A memory module comprising at least one integrated circuit comprising at least one resistivity changing memory cell,
the at least one resistivity changing memory cell comprising a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order, wherein a patterned first conductive layer and a patterned second conductive layer together form at least one structure selected from a group of structures consisting of a contact of the at least one resistivity changing memory cell memory cell, an electrode of at least one resistivity changing memory cell the memory cell, or a composite structure comprising a memory cell contact and a memory cell electrode, and wherein a ratio between a thickness of the first conductive layer and a thickness of a second conductive layer ranges between about 15 and about 30.
Specification