Method of Manufacturing a Resistivity Changing Memory Cell, Resistivity Changing Memory Cell, Integrated Circuit, and Memory Module

• US 20100032642A1
• Filed: 08/06/2008
• Published: 02/11/2010
• Est. Priority Date: 08/06/2008
• Status: Abandoned Application

• Current Assignee: Altis Semiconductor (Altis International), Qimonda AG (Infineon Technologies AG)
• Original Assignee: Altis Semiconductor (Altis International), Qimonda AG (Infineon Technologies AG)
• Inventors: Leuschner, Rainer, Park, Chanro
• Application Number:
  US12/187,258
• Publication Number:
  US 20100032642A1
• Time in Patent Office: Days
• US Class Current: 257/4
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask.

Claims

1. A method of manufacturing an integrated circuit comprising a plurality of resistivity changing memory cells, the method comprising:

forming a stack of layers comprising a resistivity changing layer, a first conductive layer, a second conductive layer, and a masking layer which are stacked above each other in this order;

patterning the second conductive layer using the masking layer as a patterning mask;

patterning the first conductive layer using the second conductive layer as a patterning mask; and

patterning the resistivity changing layer using the first conductive layer as a patterning mask.

2. The method according to claim 1, wherein patterning the first conductive layer comprises using selective etching.

3. The method according to claim 2, wherein the selective etching of the first conductive layer comprises using a low-corrosive etching substance.

4. The method according to claim 3, wherein the low-corrosive etching substance comprises a fluorine plasma.

5. The method according to claim 3, wherein patterning the second conductive layer comprises using a corrosive etching substance.

6. The method according to claim 5, wherein the corrosive etching substance comprises a chlorine plasma.

7. The method according to claim 1, further comprising patterning the masking layer, wherein patterning the masking layer comprises:

providing a photo resist layer on the masking layer;

patterning the photo resist layer using a light exposure process; and

patterning the masking layer using the photo resist layer as a patterning mask.

8. The method according to claim 1, wherein the first conductive layer comprises TaN, WN, or a combination thereof.

9. The method according to claim 1, wherein the second conductive layer comprises NiFe, Ni, Pt, Pd, Cr, Ru, or a combination thereof.

10. The method according to claim 1, wherein the masking layer comprises dielectric material.

11. The method according to claim 1, wherein a ratio between a thickness of the first conductive layer and a thickness of the second conductive layer ranges between about 15 and about 30.

12. The method according to claim 11, wherein the thickness of the first conductive layer is about 1000 Å

, and wherein the thickness of the second conductive layer is about 70 Å

.

13. The method according to claim 12, wherein a thickness of the masking layer ranges between about 50 nm and about 200 nm.

14. The method according to claim 13, wherein a thickness of the resistivity changing layer is about 100 nm.

15. The method according to claim 1, wherein the patterned first conductive layer and the patterned second conductive layer together form at least one structure selected from a group of structures consisting of a memory cell contact;

a memory cell electrode; and

a composite structure comprising a memory cell contact; and

a memory cell electrode.

16. The method according to claim 1, wherein each memory cell is a magneto-resistive memory cell, and wherein the resistivity changing layer is a magneto-resistive layer.

17. The method according to claim 1, wherein each memory cell is configured as a phase changing memory cell.

18. The method according to claim 1, wherein each memory cell is configured as a programmable metallization cell.

19. The method according to claim 1, wherein each memory cell is configured as a carbon memory cell.

20. A resistivity changing memory cell, comprising:

a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order,

wherein the first conductive layer and the second conductive layer together form at least one structure selected from the group consisting of a contact of the resistivity changing memory cell, an electrode of the resistivity changing memory cell, and a composite structure comprising a memory cell contact and a memory cell electrode, and

wherein a ratio between a thickness of the first conductive layer and a thickness of the second conductive layer ranges between about 15 and about 30.

21. The resistivity changing memory cell according to claim 20, wherein a material of the first conductive layer and a material of the second conductive layer are chosen such that the material of the first conductive layer is selectively etchable with respect to the material of the second conductive layer.

22. An integrated circuit comprising a resistivity changing memory cell, the resistivity changing memory cell comprising a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order,

wherein the first conductive layer and the second conductive layer together form at least one structure selected from a group of structures consisting of a contact of the memory cell, an electrode of the memory cell, or a composite structure comprising a memory cell contact and a memory cell electrode, and

wherein a ratio between a thickness of the first conductive layer and a thickness of the second conductive layer ranges between about 15 and about 30.

23. A memory module comprising at least one integrated circuit comprising at least one resistivity changing memory cell,

the at least one resistivity changing memory cell comprising a stack of layers, the stack of layers comprising a resistivity changing layer, a first conductive layer, and a second conductive layer which are stacked above each other in this order,

wherein a patterned first conductive layer and a patterned second conductive layer together form at least one structure selected from a group of structures consisting of a contact of the at least one resistivity changing memory cell memory cell, an electrode of at least one resistivity changing memory cell the memory cell, or a composite structure comprising a memory cell contact and a memory cell electrode, and

wherein a ratio between a thickness of the first conductive layer and a thickness of a second conductive layer ranges between about 15 and about 30.

24. The memory module according to claim 23, wherein the memory module is stackable.