INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS

• US 20100052075A1
• Filed: 12/22/2008
• Published: 03/04/2010
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Thei, Kong-Beng, Chuang, Harry, Liang, Mong-Song, Yeh, Chiung-Han, Wu, Ming-Yuan
• Granted Patent: US 8,035,165 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence

Abstract

A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a transistor formed in the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric; and

a dual first contact formed on the substrate, the dual first contact including;

a first contact feature;

a second contact feature overlying the first contact feature; and

a metal barrier layer formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

2. The semiconductor device of claim 1, wherein the first contact feature and the second contact feature are each one of copper (Cu) and tungsten (W).

3. The semiconductor device of claim 1, wherein the first contact feature has substantially a same width as the second contact feature.

4. The semiconductor device of claim 1, wherein the first contact feature has substantially a different width as the second contact feature.

5. The semiconductor device of claim 1, wherein the high-k gate dielectric includes one of HfO₂, HfZrO, and HfSiO₄.

6. The semiconductor device of claim 1, wherein the high-k gate dielectric is a multi-layer structure including one of HfO₂/SiO₂ and HfO₂/SiON.

7. The semiconductor device of claim 1, wherein the transistor further includes a capping layer formed on the high-k gate dielectric, the capping layer including one of Al₂O₃, La₂O₃, and LaSiO.

8. The semiconductor device of claim 1, wherein the transistor further includes a capping layer formed on the high-k gate dielectric, the capping layer having a multi-layer structure including one of La₂O₃/Si and La₂O₃/Al₂O₃.

9. The semiconductor device of claim 1, wherein the metal gate includes one of Al, W, Cu, WN, TiN, and combinations thereof.

10. The semiconductor device of claim 1, wherein the transistor includes a doped region, wherein the first contact feature is coupled to the doped region via a silicide feature.

11. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a transistor having a dummy gate structure;

forming a first dielectric layer over the substrate including the transistor;

forming a first contact feature in the first dielectric layer;

removing a portion of the first dielectric layer to expose a portion of the dummy gate structure;

removing the dummy gate structure and replacing it with a metal gate;

forming a second dielectric layer over the first dielectric layer; and

forming a second contact feature and a metal barrier in the second dielectric layer, the second contact feature being coupled to the first contact feature via the metal barrier.

12. The method of claim 11, wherein the removing the portion of the first dielectric layer includes performing a chemical mechanical polishing (CMP) on the first dielectric layer.

13. The method of claim 11, wherein the removing the dummy gate structure and replacing it with a metal gate includes:

performing an etch back process to remove the dummy gate structure thereby forming a trench;

filling a portion of the trench with a work function metal layer;

filling the remaining portion of the trench with a filler metal layer; and

performing a CMP process on the filler metal layer and work function metal layer to form the metal gate.

14. The method of claim 11, further comprising forming a metal layer over the second dielectric layer, the metal layer being electrically coupled to the second contact feature.

15. A semiconductor device, comprising:

a semiconductor substrate having a first region and a second region;

at least two transistors formed in the first region, the at least two transistors each having a metal gate and high-k gate dielectric; and

a dual contact structure formed in the first region between the at least two transistors, the dual contact structure including;

a first contact plug, the first contact plug having a surface that is co-planar with a surface of the metal gate; and

a second contact plug coupled to the surface of the first contact plug.

16. The semiconductor device of claim 15, further comprising a first metal layer of an interconnect structure, wherein the second contact plug is coupled to the first metal layer.

17. The semiconductor device of claim 15, wherein the second region includes a pattern density that is substantially less than a pattern density of the first region;

and

further comprising a dummy contact plug disposed in the second region, the dummy contact plug being co-planar with the first contact plug.

18. The semiconductor device of claim 17, wherein the first contact plug, second contact plug, and dummy contact plug are each one of copper (Cu) and tungsten (W).

19. The semiconductor device of claim 15, wherein the dual contact structure further includes a metal barrier layer formed on the sidewalls and bottom of the second contact plug, the metal barrier layer coupling the first contact plug to the second contact plug.

20. The semiconductor device of claim 15, wherein the dual contact structure includes a barrier metal layer formed on the sidewalls and bottom of the second contact plug, the barrier metal layer directly contacting the surface of the first contact plug.