METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY

• US 20100054383A1
• Filed: 08/28/2008
• Published: 03/04/2010
• Est. Priority Date: 08/28/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Mobin, Mohammad S., Smith, Lane A., Tracy, Paul H., Wilson, William B., Paist, Kenneth W.
• Granted Patent: US 8,407,511 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Claims

1. A method for generating one or more clock signals, said method comprising:

generating a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and

delaying at least one of said transition clock signals to generate said one or more clock signals.

2. The method of claim 1, wherein said delaying step delays said transition clock signals with respect to said data sampling clock signals.

3. The method of claim 1, wherein said generating step further comprises the step of processing a received signal using a clock and data recovery system.

4. The method of claim 1, further comprising the step of increasing a delay amount introduced by said delaying step until a predefined stopping criteria is satisfied.

5. The method of claim 4, wherein said predefined stopping criteria evaluates a noise margin.

6. The method of claim 1, wherein a delay amount introduced by said delaying step is a fixed delay amount.

7. The method of claim 1, wherein a delay amount introduced by said delaying step is a dynamic delay amount.

8. The method of claim 1, wherein a plurality of said transition clock signals have independent phase control.

9. The method of claim 1, further comprising the step of employing said one or more generated clock signals in a threshold-based decision feedback equalizer.

10. The method of claim 1, wherein said step of delaying at least one of said transition clock signals advances at least one of said data sampling clock signals.

11. A method for generating one or more clock signals, said method comprising:

generating a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and

delaying at least one of said data sampling clock signals to generate said one or more clock signals.

12. The method of claim 11, wherein said delaying step delays said data sampling clock signals with respect to said transition clock signals.

13. The method of claim 11, wherein said generating step further comprises the step of processing a received signal using a clock and data recovery system.

14. The method of claim 11, further comprising the step of increasing a delay amount introduced by said delaying step until a predefined stopping criteria is satisfied.

15. The method of claim 14, wherein said predefined stopping criteria evaluates a noise margin.

16. The method of claim 11, wherein a delay amount introduced by said delaying step is a fixed delay amount.

17. The method of claim 11, wherein a delay amount introduced by said delaying step is a dynamic delay amount.

18. The method of claim 11, wherein a plurality of said transition clock signals have independent phase control.

19. The method of claim 11 further comprising the step of employing said one or more generated clock signals in a classical decision feedback equalizer.

20. A clock and data recovery clock phase generator for generating one or more clock signals, comprising:

a clock and data recovery system for processing a received signal to generate a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and

one or more delay elements for delaying at least one of said transition clock signals to generate said one or more clock signals.

21. A clock and data recovery clock phase generator for generating one or more clock signals, comprising:

a clock and data recovery system for processing a received signal to generate a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and

one or more delay elements for delaying at least one of said data sampling clock signals to generate said one or more clock signals.