METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY
First Claim
1. A method for generating one or more clock signals, said method comprising:
- generating a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and
delaying at least one of said transition clock signals to generate said one or more clock signals.
9 Assignments
0 Petitions
Accused Products
Abstract
Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
-
Citations
21 Claims
-
1. A method for generating one or more clock signals, said method comprising:
-
generating a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of said transition clock signals to generate said one or more clock signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for generating one or more clock signals, said method comprising:
-
generating a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of said data sampling clock signals to generate said one or more clock signals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A clock and data recovery clock phase generator for generating one or more clock signals, comprising:
-
a clock and data recovery system for processing a received signal to generate a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and one or more delay elements for delaying at least one of said transition clock signals to generate said one or more clock signals.
-
-
21. A clock and data recovery clock phase generator for generating one or more clock signals, comprising:
-
a clock and data recovery system for processing a received signal to generate a plurality of transition clock signals and data sampling clock signals having a substantially uniform phase separation; and one or more delay elements for delaying at least one of said data sampling clock signals to generate said one or more clock signals.
-
Specification