SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD FOR CLOCK SIGNAL SYNCHRONIZATION
First Claim
1. A semiconductor integrated circuit comprising:
- a first circuit that operates using a first power-supply voltage supplied from a power supplying LSI;
a second circuit that operates using a second power-supply voltage;
a clock generation circuit that generates a clock signal;
a clock tree that transmits a clock generated by the clock generation circuit to the first circuit and the second circuit;
a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a path for transmitting a clock to the first circuit and a path for transmitting a clock to the second circuit along the clock tree to synchronize both clocks; and
a control circuit that notifies the power supplying LSI of change control over the first power-supply voltage,wherein the power supplying LSI is notified of a voltage change velocity for applying variable control to the first power-supply voltage in accordance with a voltage and a process condition, andwherein control is performed to match a phase between a clock supplied to the first circuit and a clock supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity.
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Accused Products
Abstract
There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
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Citations
18 Claims
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1. A semiconductor integrated circuit comprising:
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a first circuit that operates using a first power-supply voltage supplied from a power supplying LSI; a second circuit that operates using a second power-supply voltage; a clock generation circuit that generates a clock signal; a clock tree that transmits a clock generated by the clock generation circuit to the first circuit and the second circuit; a clock synchronization circuit having a plurality of delay stages that perform clock delay adjustment between a path for transmitting a clock to the first circuit and a path for transmitting a clock to the second circuit along the clock tree to synchronize both clocks; and a control circuit that notifies the power supplying LSI of change control over the first power-supply voltage, wherein the power supplying LSI is notified of a voltage change velocity for applying variable control to the first power-supply voltage in accordance with a voltage and a process condition, and wherein control is performed to match a phase between a clock supplied to the first circuit and a clock supplied to the second circuit when a voltage of the first circuit is changed at the voltage change velocity. - View Dependent Claims (2, 3, 4, 5, 13, 14, 15, 16, 17, 18)
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6. A control method for clock signal synchronization that, in a semiconductor integrated circuit comprising a first circuit using a first power-supply voltage for operation and a second circuit using a second power-supply voltage for operation, performs clock delay adjustment between a path for transmitting a clock to the first circuit and a path for transmitting a clock to the second circuit along a clock tree for transmitting a clock to the first circuit and the second circuit and synchronizes both clocks,
the method comprising: -
a voltage change process of changing the first power-supply voltage using a control circuit; and a clock synchronization process of controlling clock synchronization by performing the clock delay adjustment during the voltage change process. - View Dependent Claims (7, 8, 9)
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10. A semiconductor integrated circuit having a phase comparison circuit that compares a phase between first and second clocks provided with different signal amplitudes,
wherein the phase comparison circuit uses a first clock as an activation signal for a differential input stage, differentially amplifies a second clock based on a reference voltage equivalent to half a drive voltage for the relevant clock, and senses and latches a differential amplification result.
Specification