Multi-Thickness Semiconductor with Fully Depleted Devices and Photonic Integration

• US 20100140708A1
• Filed: 12/05/2008
• Published: 06/10/2010
• Est. Priority Date: 12/05/2008
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Pomerene, Andrew T., Carothers, Daniel N., Hill, Craig M., Vu, Vu A., Conway, Timothy J.
• Granted Patent: US 7,847,353 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Claims

1. A method for fabricating a semiconductor device, comprising:

thinning a region of a semiconductor wafer upon which the device is to be formed, thereby defining a thin region and a thick region of the wafer;

forming on the thick region one or more photonic devices and/or partially depleted electronic devices; and

forming on the thin region one or more fully depleted electronic devices.

2. The method of claim 1 further comprising:

forming an isolation area between the thin region and the thick region.

3. The method of claim 1 wherein the wafer is a silicon-on-insulator (SOI) wafer having epitaxial silicon on a thick buried oxide.

4. The method of claim 1 wherein thinning a region of a semiconductor wafer includes the use of thermal oxidation.

5. The method of claim 1 further comprising the preliminary steps of:

depositing onto the wafer a two-layer hardmask including a bottom layer of oxide and a top layer of nitride;

depositing resist over the thick region, thereby leaving the two-layer mask over the thin region exposed; and

etching the wafer to remove the exposed two-layer hardmask over the thin region.

6. The method of claim 5 wherein thinning a region of a semiconductor wafer comprises:

implanting oxygen into an epitaxial silicon layer of the wafer;

cleaning the wafer; and

annealing to convert the implanted oxygen regions into oxide.

7. The method of claim 5 wherein thinning a region of a semiconductor wafer comprises:

partially dry etching an epitaxial silicon layer of the wafer;

cleaning the wafer; and

carrying out a thermal oxidation process to consume damaged epitaxial silicon resulting from the partial dry etching.

8. The method of claim 5 wherein thinning a region of a semiconductor wafer comprises:

cleaning the wafer; and

carrying out a thermal oxidation growth process to consume underlying epitaxial silicon of the wafer.

9. The method of claim 5 wherein once the epitaxial silicon of the wafer is thinned, the method further comprises:

stripping the two-layer hardmask.

10. The method of claim 1 wherein forming on the thick region and forming on the thin region comprise:

depositing onto the wafer a two-layer hardmask including a bottom layer of oxide and a top layer of nitride;

selectively depositing resist on a hardmask area over the thick region, thereby providing an initial pattern for photonics and/or any electronics in the thick region; and

selectively depositing resist on a hardmask area over the thin region, thereby providing a pattern for fully depleted electronics in the thin region.

11. The method of claim 10 wherein forming on the thick region and forming on the thin region further comprise:

performing an initial etch to remove unmasked portions of the hardmask nitride and epitaxial silicon of the wafer; and

stripping the selectively deposited resist;

wherein the initial etch associated with the thick region is partial in that a portion of unmasked epitaxial silicon remains after the initial etch; and

wherein the initial etch associated with the thin region is a full etch in that all unmasked epitaxial silicon in the thin region is removed thereby exposing a buried oxide layer of the wafer.

12. The method of claim 11 wherein forming on the thick region and forming on the thin region further comprise:

selectively depositing resist over the thick region including the portion of unmasked epitaxial silicon remaining after the initial etch, thereby providing a pattern for a slab for photonics in the thick region;

performing a remainder of the initial etch to remove unmasked portions of the remaining epitaxial silicon of the thick region, thereby defining a slab for photonics; and

stripping the resist deposited over the thick and thin regions.

13. The method of claim 12 wherein forming on the thick region and forming on the thin region further comprise:

performing liner oxidation so that remaining epitaxial silicon is provided with an oxide layer.

14. The method of claim 12 wherein forming on the thick region further comprises:

carrying out a slab implant process.

15. The method of claim 12 wherein forming on the thick region and forming on the thin region further comprise:

performing an oxide fill process to fill one or more shallow trench isolation regions;

patterning an oxide thinning mask, thereby protecting the thick region and exposing the thin region; and

performing an oxide etch to remove a bulk of oxide above the thin region and any unprotected isolation region.

16. The method of claim 15 wherein forming on the thick region and forming on the thin region further comprise:

performing a chemical mechanical polish (CMP) process, so as to polish all oxide down to the underlying top layer of nitride; and

removing remaining nitride.

17. The method of claim 16 wherein forming on the thick region and forming on the thin region further comprise:

performing CMOS processing, including at least one of sacrificial oxide growth, body implants, gate oxide growth, polysilicon gate deposition and patterning, dielectric spacer deposition and etch back, and source/drain implants.

18. A semiconductor device, comprising:

a semiconductor wafer defining a thin region and a thick region;

one or more photonic devices and/or partially depleted electronic devices formed on the thick region; and

one or more fully depleted electronic devices formed on the thin region.

19. The device of claim 18 further comprising:

an isolation area formed between the thin region and the thick region.

20. The device of claim 18 wherein the wafer is a silicon-on-insulator (SOI) wafer having epitaxial silicon on a thick buried oxide.

21. A semiconductor device, comprising:

a semiconductor wafer defining a thin region and a thick region, wherein the wafer is a silicon-on-insulator (SOI) wafer having epitaxial silicon on a thick buried oxide;

one or more photonic devices and/or partially depleted CMOS devices formed on the thick region;

one or more fully depleted CMOS devices formed on the thin region; and

an isolation area formed between the thin region and the thick region.