COMPILER IMPLEMENTATION OF LOCK/UNLOCK USING HARDWARE TRANSACTIONAL MEMORY
First Claim
1. A method comprising:
- examining one or more program instructions;
identifying a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;
replacing the TSR with a first portion of code and a second portion of code; and
setting an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.
2 Assignments
0 Petitions
Accused Products
Abstract
A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.
-
Citations
20 Claims
-
1. A method comprising:
-
examining one or more program instructions; identifying a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory; replacing the TSR with a first portion of code and a second portion of code; and setting an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A compiler comprising:
-
a processor core selection unit configured to assign software threads to waiting hardware threads; a code generator; and an optimizer, wherein the optimizer is configured to; examine one or more program instructions; identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory; replace the TSR with a first portion of code and a second portion of code; and set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A computer readable storage medium storing program instructions operable to parallelize code combined with hardware transactional memory support, wherein the program instructions are executable to:
-
examine one or more program instructions; identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory; replace the TSR with a first portion of code and a second portion of code; and set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution. - View Dependent Claims (18, 19, 20)
-
Specification