Compiler implementation of lock/unlock using hardware transactional memory

• US 8,612,929 B2
• Filed: 12/10/2008
• Issued: 12/17/2013
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Kalogeropulos, Spiros, Song, Yonghong, Tirumalai, Partha P.
• Primary Examiner(s): Zhen, Li B
• Assistant Examiner(s): Kia, Arshia S
• Application Number:
  US12/331,950
• Publication Number:
  US 20100146480A1
• Time in Patent Office: 1,833 Days
• Field of Search: 717/106
• US Class Current: 717/106
• CPC Class Codes: G06F 8/458 Synchronisation, e.g. post-wait, barriers, locks synchronisation among tasks G06F9/52
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.

Claims

1. A method executable by a processor for parallelizing code using transaction memory comprising:

examining one or more program instructions;

identifying a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

performing no transformation of the TSR, in response to predicting a transformed TSR will fail during execution; and

in response to predicting a transformed TSR will not fail during execution;

replacing the TSR with a first portion of code and a second portion of code, wherein the first portion of code is configured to access the shared region without lock and unlock function calls and without software transactional memory semantics;

executing the first portion of code without disabling existing hardware transactional memory support; and

said first portion calling said second portion to perform a failure handling routine in response to an indication a failure occurs within said first portion.

2. The method as recited in claim 1, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein said first portion of code comprises a replacement command pair in place of the lock and unlock function calls.

3. The method as recited in claim 2, further comprising generating code for said first portion operable to:

initially access said shared region without the lock and unlock function calls and without software transactional memory semantics during the accessing; and

ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

4. The method as recited in claim 3, wherein said code to ensure is operable to determine a predetermined safe value is stored in a predetermined memory location, wherein the predetermined memory location is accessible by both user-specified transactions and transactions within hardware transactional memory support.

5. The method as recited in claim 2, further comprising generating code for said second portion of code operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.

6. The method as recited in claim 5, wherein setting said indication further comprises identifying one or more of the following:

the TSR comprises a predetermined instruction type, the TSR exceeds available space in a store buffer, and the TSR comprises more than a predetermined number of instructions.

7. The method as recited in claim 6, wherein setting said indication further comprises utilizing program profiling information.

8. The method as recited in claim 2, wherein said first portion of code comprises hardware transactional memory primitives.

9. A computer system comprising:

a processor; and

a memory configured to store first program instructions and second program instructions;

wherein the processor is configured assign software threads to waiting hardware threads and to execute said first program instructions to;

examine said second program instructions;

identify a transaction synchronization region (TSR) within said second program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

perform no transformation of the TSR, in response to predicting a transformed TSR will fail during execution; and

in response to predicting a transformed TSR will not fail during execution;

replace the TSR with a first portion of code and a second portion of code, wherein the first portion of code is configured to access the shared region without lock and unlock function calls and without software transactional memory semantics; and

execute the first portion of code without disabling existing hardware transactional memory support; and

cause said first portion to call said second portion to perform a failure handling routine in response to an indication a failure occurs within said first portion.

10. The computer system as recited in claim 9, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein the code generator is configured to generate said first portion of code to include a replacement command pair in place of the lock and unlock function calls.

11. The computer system as recited in claim 10, wherein the code generator is configured to generate code for said first portion operable to:

initially access said shared region without the lock and unlock function calls and without software transactional memory semantics during the accessing; and

ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

12. The computer system as recited in claim 11, wherein said code to ensure is operable to determine a predetermined safe value is stored in a predetermined memory location, wherein the predetermined memory location is accessible by both user-specified transactions and transactions within hardware transactional memory support.

13. The computer system as recited in claim 10, wherein the code generator is configured to generate code for said second portion operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.

14. The computer system as recited in claim 13, wherein the optimizer, in order to set said indication, is operable to identify one or more of the following:

the TSR comprises a predetermined instruction type, the TSR exceeds available space in a store buffer, and the TSR comprises more than a predetermined number of instructions.

15. The computer system as recited in claim 14, wherein the optimizer, in order to set said indication, utilizes program profiling information.

16. The computer system as recited in claim 10, said first portion of code comprises hardware transactional memory primitives.

17. A non-transitory computer readable storage medium storing program instructions operable to parallelize code combined with hardware transactional memory support, wherein the program instructions are executable to:

examine one or more program instructions;

identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

perform no transformation of the TSR, in response to predicting a transformed TSR will fail during execution; and

in response to predicting a transformed TSR will not fail during execution;

replace the TSR with a first portion of code and a second portion of code, wherein the first portion of code is configured to access the shared region without lock and unlock function calls and without software transactional memory semantics; and

execute the first portion of code without disabling existing hardware transactional memory support; and

cause said first portion to call said second portion to perform a failure handling routine in response to an indication a failure occurs within said first portion.

18. The storage medium as recited in claim 17, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein said first portion of code comprises a replacement command pair in place of the lock and unlock function calls.

19. The storage medium as recited in claim 18, wherein the program instructions are further executable to generate code for said first portion operable to:

initially access said shared region without the lock and unlock function calls and without software transactional memory semantics during the accessing; and

ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

20. The storage medium as recited in claim 18, wherein the program instructions are further executable to generate code for said second portion of code operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.