SEMICONDUCTOR STORAGE DEVICE

• US 20100219483A1
• Filed: 02/03/2010
• Published: 09/02/2010
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Arai, Shintaro
• Granted Patent: US 8,378,425 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.

Claims

1. A semiconductor storage device comprising a static type memory cell in which six MOS transistors are arrayed on a dielectric film formed on a substrate, characterized in that:

each of the six MOS transistors comprises a source diffusion layer, a drain diffusion layer, a pillar-shaped semiconductor layer disposed between the source and drain diffusion layers, and a gate formed along a sidewall of the pillar-shaped semiconductor layer, wherein the source diffusion layer, the drain diffusion layer and the pillar-shaped semiconductor layer are arranged on the dielectric film formed on the substrate, hierarchically in a vertical direction, and wherein the six MOS transistors function as respective ones of first and second NMOS access transistors each operable to allow access to the memory cell, first and second NMOS driver transistors each operable to drive a storage node to hold data in the memory cell, and first and second PMOS load transistors each operable to supply electric charges to hold data in the memory cell, and wherein;

the first NMOS access transistor, the first NMOS driver transistor and the first PMOS load transistor are arrayed in adjacent relation to each other;

the second NMOS access transistor, the second NMOS driver transistor and the second PMOS load transistor are arrayed in adjacent relation to each other;

the source or drain diffusion layers of the first NMOS access transistor, the first NMOS driver transistor and the first PMOS load transistor, are arranged on the dielectric film as three first diffusion layers to serve as a first storage node for holding data therein, wherein the first diffusion layers are connected to each other through a first silicide layer formed on respective surfaces of the first diffusion layers; and

the source or drain diffusion layers of the second NMOS access transistor, the second NMOS driver transistor and the second PMOS load transistor, are arranged on the dielectric film as three second diffusion layers to serve as a second storage node for holding data therein, wherein the second diffusion layers are connected to each other through a second silicide layer formed on respective surfaces of the second diffusion layers.

2. The semiconductor storage device as defined in claim 1, characterized in that:

a gate line extending from the respective gates of the driver transistor and the load transistor each formed on corresponding ones of the first diffusion layers serving as the first storage node is connected to a common contact; and

a gate line extending from the respective gates of the driver transistor and the load transistor each formed on corresponding ones of the second diffusion layers serving as the second storage node is connected to a common contact.

3. The semiconductor storage device as defined in claim 1, characterized in that a peripheral length of the sidewall in each of the pillar-shaped semiconductor layers forming the access transistors, the pillar-shaped semiconductor layers forming the driver transistors and the pillar-shaped semiconductor layers forming the load transistors, is determined based on an operation margin during reading and an operation margin during writing.

4. The semiconductor storage device as defined in claim 2, characterized in that a peripheral length of the sidewall in each of the pillar-shaped semiconductor layers forming the access transistors, the pillar-shaped semiconductor layers forming the driver transistors and the pillar-shaped semiconductor layers forming the load transistors, is determined based on an operation margin during reading and an operation margin during writing.

5. The semiconductor storage device as defined in claim 1, characterized in that a contact to be formed on a gate line extending from a gate electrode of at least one of the first and second NMOS access transistors is shared as a contact to be formed on a gate line extending from a gate electrode of an NMOS access transistor in an adjacent memory cell.

6. The semiconductor storage device as defined in claim 2, characterized in that a contact to be formed on a gate line extending from a gate electrode of at least one of the first and second NMOS access transistors is shared as a contact to be formed on a gate line extending from a gate electrode of an NMOS access transistor in an adjacent memory cell.

7. The semiconductor storage device as defined in claim 1, characterized in that the pillar-shaped semiconductor layers are arrayed in a hexagonal lattice pattern.

8. The semiconductor storage device as defined in claim 2, characterized in that the pillar-shaped semiconductor layers are arrayed in a hexagonal lattice pattern.

9. The semiconductor storage device as defined in claim 1, characterized in that:

a gate line extending from the respective gates of the driver transistor and the load transistor each formed on corresponding ones of the first diffusion layers serving as the first storage node is connected to one of the second diffusion layers serving as the second storage node, through a common contact; and

a gate line extending from the respective gates of the driver transistor and the load transistor each formed on corresponding ones of the second diffusion layers serving as the second storage node is connected to one of the first diffusion layers serving as the first storage node, through a common contact.

10. The semiconductor storage device as defined in claim 1, characterized in that the six MOS transistors are arranged on the dielectric film in a three-row by two-column array, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 2nd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 3rd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 3rd row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 2nd row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 1st row and the 2nd column.

11. The semiconductor storage device as defined in claim 1, characterized in that the six MOS transistors are arranged on the dielectric film in a three-row by two-column array, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 3rd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 3rd row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 1st row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 2nd row and the 2nd column.

12. The semiconductor storage device as defined in claim 1, characterized in that the six MOS transistors are arranged on the dielectric film in a three-row by two-column array, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 3rd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 1st row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 3rd row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 2nd row and the 2nd column.

13. The semiconductor storage device as defined in claim 9, characterized in that a contact to be formed on a gate line extending from the gate of the first NMOS access transistor is shared as a contact to be formed on a gate line extending from the gate of the second NMOS access transistor.

14. The semiconductor storage device as defined in claim 1, characterized in that the six MOS transistors are arranged on the dielectric film in a two-row by three-column array, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 2nd row and the 2nd column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 2nd row and the 3rd column;

the second PMOS load transistor is arranged at an intersection of the 1st row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 1st row and the 3rd column.