REDUCING SILICIDE RESISTANCE IN SILICON/GERMANIUM-CONTAINING DRAIN/SOURCE REGIONS OF TRANSISTORS

• US 20100244107A1
• Filed: 03/30/2010
• Published: 09/30/2010
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: WIATR, Maciej, Kronholz, Stephan, PAPAGEORGIOU, Vassilios
• Granted Patent: US 8,124,467 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon layer may be formed on the silicon/germanium alloy, possibly including a further strain-inducing atomic species other than germanium, in order to provide a high strain component while also providing superior conditions during the silicidation process.

Claims

1. A method, comprising:

forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor;

forming a strain-inducing silicon/germanium alloy in said cavity, said silicon/germanium alloy having a first silicon concentration;

forming a silicon-containing semiconductor material on said strain-inducing silicon/germanium alloy, said silicon-containing semiconductor material having a second silicon concentration that is greater than said first silicon concentration;

forming drain and source regions at least partially in said silicon/germanium alloy and said silicon-containing semiconductor material; and

forming a metal silicide in said silicon-containing semiconductor material.

2. The method of claim 1, wherein said silicon-containing semiconductor material comprises germanium.

3. The method of claim 2, wherein a germanium concentration is less than approximately 1 atomic percent.

4. The method of claim 1, wherein said silicon-containing semiconductor material is formed so as to contain an atomic species having a covalent radius that is greater than a covalent radius of germanium.

5. The method of claim 4, wherein said atomic species comprises tin.

6. The method of claim 4, wherein forming said silicon-containing semiconductor material comprises performing a selective epitaxial growth process.

7. The method of claim 1, wherein said silicon-containing semiconductor material and said silicon/germanium alloy are formed in situ.

8. The method of claim 1, wherein forming said silicon-containing semiconductor material comprises forming a silicon layer on said silicon/germanium alloy and introducing said atomic species into said silicon layer by performing an ion implantation process.

9. The method of claim 1, wherein forming said metal silicide comprises adapting a thickness of said silicon-containing semiconductor material so as to create said metal silicide within said silicon-containing semiconductor material.

10. The method of claim 1, wherein a germanium concentration of said silicon/germanium alloy is approximately 25 atomic percent of higher.

11. The method of claim 1, wherein forming said metal silicide comprises depositing at least one of nickel and platinum and performing a heat treatment to initiate a chemical reaction of said at least one of nickel and platinum and the silicon of said silicon-containing semiconductor material.

12. A method, comprising:

forming a silicon-containing semiconductor material on a silicon/germanium alloy formed in an active region of a P-type transistor, said silicon-containing semiconductor material having a germanium concentration that is less than a germanium concentration of said silicon/germanium alloy; and

forming a metal silicide locally restricted to said silicon-containing semiconductor material.

13. The method of claim 12, wherein said silicon/germanium alloy and said silicon-containing semiconductor material are formed in situ by performing a selective epitaxial growth process.

14. The method of claim 12, further comprising forming drain and source regions in said active region after forming said silicon/germanium alloy and prior to forming said silicon-containing semiconductor material.

15. The method of claim 12, wherein forming said silicon-containing semiconductor material comprises incorporating an atomic species into a silicon base material, wherein said atomic species has a greater covalent radius compared to germanium.

16. The method of claim 15, wherein said atomic species is incorporated by performing a selective epitaxial growth process using a precursor containing silicon and said atomic species.

17. The method of claim 15, wherein said atomic species is incorporated by performing an ion implantation process.

18. The method of claim 15, wherein said atomic species comprises tin.

23. The semiconductor device of claim 16, wherein a gate length of said transistor is approximately 50 nm or less.

19. A semiconductor device, comprising:

a gate electrode structure formed above a silicon-containing semiconductor region;

drain and source regions formed in said silicon-containing semiconductor region;

a silicon/germanium alloy formed at least partially in at least one of said drain region and said source region, said silicon/germanium alloy having a first germanium concentration; and

a metal silicide at least partially formed in said drain and source regions, said metal silicide having a second germanium concentration that is less than said first germanium concentration.

20. The semiconductor device of claim 19, wherein said first germanium concentration is approximately 25 atomic percent and higher relative to a silicon concentration in said silicon/germanium alloy and wherein said second germanium concentration is approximately 5 atomic percent or less relative to a silicon concentration of said metal silicide.

21. The semiconductor device of claim 19, wherein said metal silicide comprises tin and wherein a concentration of tin in said silicon/germanium alloy is less than in said metal silicide.

22. The semiconductor device of claim 19, wherein said metal silicide comprises at least one of nickel and platinum.