MICRO PIEZORESISTIVE PRESSURE SENSOR AND MANUFACTURING METHOD THEREOF

• US 20100251826A1
• Filed: 04/21/2008
• Published: 10/07/2010
• Est. Priority Date: 12/05/2007
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Youn Tae, Choi, Chang Auck, Lee, Myung Lae, Lee, Sung Sik, Je, Chang Han, Hwang, Gunn, Moon, Seok Hwan, Jung, Sung Hae
• Granted Patent: US 8,261,617 B2
• Time in Patent Office: Days
• US Class Current: 73/727
• CPC Class Codes: B81C 1/00047 Cavities
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: Y10T 29/42 Piezoelectric device making
• CPC Class Codes: Y10T 29/49 Method of mechanical manufacture

Abstract

A micro semiconductor-type pressure sensor and a manufacturing method thereof are provided. The micro semi-conductor-type pressure sensor is implemented by etching a cavity-formation region of a substrate to form a plurality of trenches, oxidizing the plurality of trenches through a thermal oxidation process to form a cavity-formation oxide layer, forming a membrane-formation material layer on upper portions of the cavity-formation oxide layer and the substrate, forming a plurality of etching holes in the membrane-formation material layer, removing the cavity-formation oxide layer through the plurality of etching holes to form a cavity buried in the substrate, forming a membrane reinforcing layer on an upper portion of the membrane-formation material layer to form a membrane for closing the cavity, and forming sensitive films made of a piezoresisive material on an upper portion of the membrane.

Claims

1. A micro piezoresisive pressure sensor comprising:

a silicon substrate;

a cavity buried in the silicon substrate;

a membrane which has a laminated structure formed on an upper portion of the silicon substrate to close the cavity; and

sensitive films which are constructed with a piezoresisive material formed on an upper portion of the membrane.

2. The micro piezoresisive pressure sensor of claim 1, further comprising one or more semiconductor integrated devices which are formed in portions of the silicon substrate excluding a portion where the cavity is formed.

3. The micro piezoresisive pressure sensor of claim 2, wherein the semiconductor integrated devices are CMOS devices.

4. The micro piezoresisive pressure sensor of claim 3, wherein the cavity and the membrane are formed together by using a CMOS device manufacturing process for manufacturing the semiconductor integrated devices.

5. The micro piezoresisive pressure sensor of claim 4, wherein the cavity is formed through a trench etching process, a field oxide layer forming process for device isolation, and a silicon oxide removing process in the CMOS device manufacturing process.

6. The micro piezoresisive pressure sensor of claim 4, wherein the membrane is formed with an insulating-layer laminated structure of a polysilicon layer and a silicon nitride layer or a silicon oxide layer.

7. The micro piezoresisive pressure sensor of claim 6, wherein the membrane is formed through a diffusing thermal treatment process for source and drain and a silicon oxide layer forming process for insulation in the CMOS device manufacturing process.

8. A method of manufacturing a micro piezoresisive pressure sensor, comprising:

forming a plurality of trenches by etching a cavity-formation region of a substrate;

forming a cavity-formation oxide layer in the cavity-formation region of the substrate by oxidizing the plurality of trenches through a thermal oxidation process;

forming a membrane-formation material layer on upper portions of the cavity-formation oxide layer and the substrate;

forming a plurality of etching holes in the membrane-formation material layer formed on the cavity-formation oxide layer;

forming a cavity buried in the substrate by removing the cavity-formation oxide layer through the plurality of etching holes;

forming a membrane reinforcing layer on an upper portion of the membrane-formation material layer and forming a membrane for closing the cavity; and

forming sensitive films which are constructed with a piezoresisive material on an upper portion of the membrane.

9. The method of claim 8, wherein the substrate is made of a silicon material.

10. The method of claim 9, further comprising forming a stress buffer layer in a device region for forming a semiconductor integrated device in the substrate, before the forming of the plurality of trenches.

11. The method of claim 10, further comprising forming a field oxide layer for device isolation between the semiconductor integrated devices in the device region of the substrate.

12. The method of claim 11, wherein the cavity-formation oxide layer and the field oxide layer are formed together in the same thermal oxidation process.

13. The method of claim 12, wherein a width of the trenches is 2 μ

m or less, and an interval between the trenches is 0.56 to 0.60 times the width of the trenches.

14. The method of claim 11, further comprising removing the stress buffer layer formed in the device region through a wet etching process and performing a polishing process including a chemical mechanical polishing (CMP) process for surface planarization, after the forming of the cavity-formation oxide layer and the field oxide layer.

15. The method of claim 14, further comprising forming a gate, a source, and a drain for forming semiconductor integrated devices between field oxide layers, after the removing of the stress buffer layer.

16. The method of claim 14, further comprising reducing a diameter of the plurality of etching holes through volume expansion due to partial oxidation of the membrane-formation material layer by performing thermal oxidation on the membrane-formation material layer in which the plurality of etching holes are formed, after the forming of the cavity buried in the substrate.

17. The method of claim 16, wherein the membrane-formation material layer is made of polysilicon.

18. The method of claim 17, wherein the forming of the cavity buried in the substrate by removing the cavity-formation oxide layer is removing the cavity-formation oxide layer through an oxide-layer wet etching method using a hydro fluoric solution or an oxide-layer dry etching method based on a large difference in an etch ratio between the polysilicon and silicon oxide layer.

19. The method of claim 16, wherein the thermal oxidation of the membrane-formation material layer is performed by using a diffusing thermal treatment process for the source and the drain.

20. The method of claim 19, wherein the diameter of the plurality of etching holes is in a range of 0.5 to 1.5 μ

m.

21. The method of claim 16, further comprising forming an insulating layer on upper portions of the source, the drain, and the gate.

22. The method of claim 21, wherein the insulating layer and the membrane reinforcing layer are formed together by using the same material through the same process.

23. The method of claim 22, wherein the insulating layer and the membrane reinforcing layer are constructed with an insulating layer including a silicon oxide layer or a silicon nitride layer.

24. The method of claim 16, further comprising forming a chip-protection oxide layer, opening a portion of the chip-protection oxide layer, and forming metal layers for electrical connection between the sensitive films and the semi-conductor integrated devices, after the forming of the insulating layer and the sensitive films.