ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS

• US 20100270535A1
• Filed: 05/18/2010
• Published: 10/28/2010
• Est. Priority Date: 12/22/2005
• Status: Abandoned Application

• Current Assignee: Mears Technologies Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Mears, Robert J., Huang, Xiangyang, Yiptong, Jean Augustin Chan Sow Fook, Stephenson, Robert John
• Application Number:
  US12/782,211
• Publication Number:
  US 20100270535A1
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G01J 5/34 using capacitors, e.g. pyroelectric capacitors
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H03H 9/02543 Characteristics of substrate, e.g. cutting angles
• CPC Class Codes: H10N 15/15 Selection of materials
• CPC Class Codes: H10N 30/852 Composite materials, e.g. having 1-3 or 2-2 type connectivity

Abstract

A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.

Claims

1-27. -27. (canceled)

28. A electronic device comprising:

an electrically poled superlattice comprising a plurality of stacked groups of layers;

each group of layers of said electrically poled superlattice comprising a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween; and

at least one electrode for selectively changing the poling of said electrically poled superlattice.

29. The electronic device of claim 28 wherein said at least one electrode is also for determining a poling of said electrically poled superlattice.

30. The electronic device of claim 28 further comprising:

a semiconductor substrate;

spaced apart source and drain regions in said semiconductor substrate and defining a channel region therebetween; and

a gate overlying said channel region and comprising at least one gate layer adjacent said electrically poled superlattice.

31. The electronic device of claim 30 wherein said electrically poled superlattice overlies the channel region, and wherein said at least one gate layer overlies said electrically poled superlattice.

32. The electronic device of claim 28 wherein said gate further comprises a gate insulating layer between said semiconductor substrate and said at least one gate layer.

33. The electronic device of claim 28 wherein each base semiconductor portion comprises silicon.

34. The electronic device of claim 28 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

35. The electronic device of claim 28 wherein each non-semiconductor monolayer comprises oxygen.

36. The electronic device of claim 28 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

37. A memory device comprising:

an array of memory cells defining a non-volatile memory, each memory cell comprising

an electrically poled superlattice comprising a plurality of stacked groups of layers,

each group of layers of said electrically poled superlattice comprising a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon,

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween, and

at least one electrode for selectively changing the poling of said electrically poled superlattice.

38. The memory device of claim 37 wherein said at least one electrode is also for determining a poling of said electrically poled superlattice.

39. The memory device of claim 37 wherein each memory cell further comprises:

a semiconductor substrate;

spaced apart source and drain regions in said semiconductor substrate and defining a channel region therebetween; and

a gate overlying said channel region and comprising at least one gate layer adjacent said electrically poled superlattice.

40. The memory device of claim 39 wherein said electrically poled superlattice overlies the channel region, and wherein said at least one gate layer overlies said electrically poled superlattice.

41. The memory device of claim 39 wherein said gate further comprises a gate insulating layer between said semiconductor substrate and said at least one gate layer.

42. A method for making an electronic device comprising:

forming a superlattice comprising a plurality of stacked groups of layers and electrically poling the superlattice;

each group of layers of the electrically polled superlattice comprising a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween; and

coupling at least one electrode to the electrically polled superlattice for selective poling thereof.

43. The method of claim 42 wherein the at least one electrode is also for determining a poling of the electrically polled superlattice.

44. The method of claim 42 further comprising:

providing a semiconductor substrate;

forming spaced apart source and drain regions in the semiconductor substrate and defining a channel region therebetween; and

forming a gate overlying the channel region and comprising at least one gate layer adjacent the electrically polled superlattice.

45. The method of claim 44 wherein the electrically polled superlattice overlies the channel region, and wherein the at least one gate layer overlies the electrically polled superlattice.

46. The method of claim 44 wherein the gate further comprises a gate insulating layer between the semiconductor substrate and the at least one gate layer.

47. The method of claim 42 wherein each base semiconductor portion comprises silicon.

48. The method of claim 42 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

49. The method of claim 42 wherein each non-semiconductor monolayer comprises oxygen.

50. The method of claim 42 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.