MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE

• US 20100318718A1
• Filed: 06/11/2009
• Published: 12/16/2010
• Est. Priority Date: 06/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leinwander, Mark, Eilert, Sean
• Granted Patent: US 9,123,409 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Claims

1. A hierarchical memory device, comprising:

a Phase Change Memory (PCM);

multiple interfaces having different memory formats; and

an input port and an output port to connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure, wherein standard non-hierarchical memory devices attach to the output port of the hierarchical memory device.

2. The hierarchical memory device of claim 1 wherein the multiple interfaces include a RAM interface, a NAND interface, a network interface, a storage interface and a peripheral interface.

3. The hierarchical memory device of claim 1 further configurable to operate as an IO mapped, memory mapped, or memory mapped IO device.

4. The hierarchical memory device of claim 1 to switch traffic between an upstream port and a downstream port in the hierarchical tree structure.

5. The hierarchical memory device of claim 1 to interpret traffic in the daisy-chain hierarchy to determine whether the traffic is for the hierarchical memory device or for a downstream/upstream node.

6. A hierarchical memory device for use in a memory subsystem, comprising:

Phase Change Memory (PCM); and

a processor core to execute algorithms for wear leveling, caching, error detection and correction, and data manipulation to manage performance and reliability;

wherein the hierarchical memory device is configurable to operate as an IO mapped, memory mapped, or memory mapped IO device.

7. The hierarchical memory device of claim 6 wherein the hierarchical memory device operates as a sector based device.

8. The hierarchical memory device of claim 6 wherein the hierarchical memory device is connected with other hierarchical memory devices in a daisy-chain configuration.

9. The hierarchical memory device of claim 6 wherein the hierarchical memory device is connected with other hierarchical memory devices in a tree structure.

10. A hierarchical memory device having a buffer memory, comprising:

a Phase Change Memory (PCM) array;

a RAM interface;

a NAND interface to extract command information to adjust a data rate between the NAND interface and the buffer memory based on the command;

a network interface to support signaling rates and data packet transmissions over communication links;

a storage interface; and

a peripheral interface.

11. The hierarchical memory device of claim 10 wherein the RAM interface provides communication between a host and the memory device as a Double-Data-Rate Random Access Memory (DDR RAM).

12. The hierarchical memory device of claim 10 wherein the RAM interface provides communication between a host and the memory device as a Double-Data-Rate three Synchronous Dynamic Random Access Memory (DDR3 SDRAM).

13. The hierarchical memory device of claim 10 wherein the RAM interface is a reduced power interface Low Power Double-Data-Rate (LPDDR).

14. The hierarchical memory device of claim 10 wherein the NAND interface operates as sector based.

15. The hierarchical memory device of claim 10 wherein the network interface supports an Ethernet protocol.

16. The hierarchical memory device of claim 10 wherein the network interface supports an InfiniBand point-to-point bidirectional serial link.

17. The hierarchical memory device of claim 10 wherein the network interface supports 802.11 communication links.

18. The hierarchical memory device of claim 10 wherein the storage interface is a Serial ATA (SATA) storage interface that allows communication between a host bus and mass storage devices.

19. The hierarchical memory device of claim 10 wherein the storage interface is a Serial-Attached SCSI (SAS) that is a point-to-point serial interface that links memory device to a disk drive.

20. The hierarchical memory device of claim 10 wherein the storage interface supports a Fibre Channel Protocol (FCP).

21. A packaged memory device, comprising:

a hierarchical memory having Phase Change Memory (PCM) arrays and multiple interfaces to handle different memory formats including a NAND interface; and

first and second NAND devices connected to output ports of the hierarchical memory device.

22. The packaged memory device of claim 21 further comprising a Random Access Memory (RAM) having address ports and data ports in common with the hierarchical memory.

23. A packaged memory device, comprising:

first and second hierarchical memory each having Phase Change Memory (PCM) arrays and multiple interfaces to handle different memory formats and output ports to link to NAND devices.

24. A packaged memory device, comprising:

first and second hierarchical memory each having Phase Change Memory (PCM) arrays, multiple interfaces to handle different memory formats, and output ports;

first and second NAND devices connected to the output ports of the first hierarchical memory; and

third and fourth NAND devices connected to the output ports of the second hierarchical memory.

25. The packaged memory device of claim 24 further comprising a Random Access Memory (RAM) having address ports and data ports in common with the first and second hierarchical memory.