MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE
First Claim
Patent Images
1. A hierarchical memory device, comprising:
- a Phase Change Memory (PCM);
multiple interfaces having different memory formats; and
an input port and an output port to connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure, wherein standard non-hierarchical memory devices attach to the output port of the hierarchical memory device.
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Abstract
A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.
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Citations
25 Claims
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1. A hierarchical memory device, comprising:
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a Phase Change Memory (PCM); multiple interfaces having different memory formats; and an input port and an output port to connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure, wherein standard non-hierarchical memory devices attach to the output port of the hierarchical memory device. - View Dependent Claims (2, 3, 4, 5)
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6. A hierarchical memory device for use in a memory subsystem, comprising:
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Phase Change Memory (PCM); and a processor core to execute algorithms for wear leveling, caching, error detection and correction, and data manipulation to manage performance and reliability;
wherein the hierarchical memory device is configurable to operate as an IO mapped, memory mapped, or memory mapped IO device. - View Dependent Claims (7, 8, 9)
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10. A hierarchical memory device having a buffer memory, comprising:
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a Phase Change Memory (PCM) array; a RAM interface; a NAND interface to extract command information to adjust a data rate between the NAND interface and the buffer memory based on the command; a network interface to support signaling rates and data packet transmissions over communication links; a storage interface; and a peripheral interface. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A packaged memory device, comprising:
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a hierarchical memory having Phase Change Memory (PCM) arrays and multiple interfaces to handle different memory formats including a NAND interface; and first and second NAND devices connected to output ports of the hierarchical memory device. - View Dependent Claims (22)
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23. A packaged memory device, comprising:
first and second hierarchical memory each having Phase Change Memory (PCM) arrays and multiple interfaces to handle different memory formats and output ports to link to NAND devices.
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24. A packaged memory device, comprising:
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first and second hierarchical memory each having Phase Change Memory (PCM) arrays, multiple interfaces to handle different memory formats, and output ports; first and second NAND devices connected to the output ports of the first hierarchical memory; and third and fourth NAND devices connected to the output ports of the second hierarchical memory. - View Dependent Claims (25)
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Specification