BATTERY BACKUP SYSTEM WITH SLEEP MODE
First Claim
Patent Images
1. An apparatus comprising:
- a charger circuit configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and
a control circuit configured to generate said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said control circuit enters a sleep mode in said power down state and (iii) said control circuit disconnects operating power from said charger circuit in said power down state.
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Abstract
The present invention concerns an apparatus comprising a charger circuit and a control circuit. The charger circuit may be configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal. The control circuit may be configured to generate the first charge signal and the second charge signal in response to a first battery signal and a second battery signal. The control circuit may enter a power down state in response to the host control signal initiating the power down state.
20 Citations
20 Claims
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1. An apparatus comprising:
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a charger circuit configured to generate a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and a control circuit configured to generate said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said control circuit enters a sleep mode in said power down state and (iii) said control circuit disconnects operating power from said charger circuit in said power down state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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means for generating a first power down control signal and a second power down control signal in response to (i) a first charge signal, (ii) a second charge signal, (iii) a supply voltage, and (iv) a host control signal; and means for generating said first charge signal and said second charge signal in response to a first battery signal and a second battery signal, wherein (i) said apparatus enters a power down state in response to said host control signal initiating said power down state, (ii) said means for generating said first charge signal and said second charge signal enters a sleep mode in said power down state and (iii) said means for generating said first charge signal and said second charge signal disconnects operating power from said means for generating said first power down control signal and said second power down control signal in said power down state.
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12. An apparatus comprising:
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an input circuit configured to generate a simulated power supply signal having an enabled state and a disabled state in response to a main power source and a host control signal received from a host bus; and a charger circuit configured to avoid a power not good condition that disables operation of said charger circuit when said simulated power supply signal is in said enabled state, wherein (A) said charger circuit (i) is configured to charge a first battery and a second battery when said main power source is present, and (ii) protects an over voltage condition of said main power source from damaging said host bus and (B) said power not good condition occurs when initializing a power up sequence of said apparatus with said first battery unavailable, said second battery unavailable and said simulated power supply signal in said disabled state. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification