RFID Device Time Synchronization From A Public Source
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Abstract
A radio frequency identification (RFID) device includes an antenna linked to a receiving circuit, the antenna tuned to receive a radio frequency (RF) time-code signal from a public source, a controller circuit and an internal clock linked to the receiving circuit, a microcontroller linked to the receiving circuit, a memory linked to the microcontroller, and a battery linked to and powering the receiving circuit, controller circuit, internal clock, microcontroller and memory.
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Citations
7 Claims
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1. (canceled)
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2. A system comprising:
a radio frequency identification (RFID) device comprising; an antenna tuned to receive a radio frequency (RF) position signal from a public source; a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received RF position signal into a digital position bit stream; a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital position bit stream; and an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded position bit stream received from the controller circuit.
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3. The system of claim 3, further comprising:
an RFID interrogator configured to interrogate the RFID device and receive in response an RFID identification and a time stamp, wherein the time stamp corresponds to the time maintained by the internal clock.
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4. The system of claim 4, further comprising:
a subsystem linked to the RFID interrogator, wherein the subsystem is configured to store the RFID identification and the time stamp.
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5. A system comprising:
a radio frequency identification (RFID) device comprising; an antenna tuned to receive a global positioning system (GPS) speed signal from a public source; a receiving circuit linked to the antenna, wherein the receiving circuit is configured to convert the received GPS speed signal into a digital speed bit stream; a controller circuit linked to the receiving circuit, wherein the controller circuit is configured to decode the digital speed bit stream; and an internal clock linked to the controller circuit, wherein a time maintained by the internal clock is updated based on the decoded speed bit stream received from the controller circuit. - View Dependent Claims (6, 7)
Specification