SEMICONDUCTOR DEVICES AND DYNAMIC RANDOM ACCESS MEMORY DEVICES INCLUDING BURIED GATE PATTERN WITH HIGH-K CAPPING LAYER
First Claim
1. A semiconductor device, comprising:
- a substrate having a gate trench;
a buried gate electrode partially filling the gate trench;
a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material layer that directly contacts an upper surface of the buried gate electrode;
source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode; and
a gate insulation layer interposed between the gate trench and the buried gate electrode.
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Accused Products
Abstract
Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a substrate having a gate trench; a buried gate electrode partially filling the gate trench; a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material layer that directly contacts an upper surface of the buried gate electrode; source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode; and a gate insulation layer interposed between the gate trench and the buried gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A dynamic random access memory (DRAM), comprising:
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an impurity layer in a substrate; a gate trench in the impurity layer and dividing the impurity layer into respectively separated source/drain regions; a buried gate electrode partially filling the gate trench; a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material; an interlayer insulation layer covering the capping layer pattern and the source/drain regions; a storage electrode over the interlayer insulation layer and electrically connected to one of the source/drain regions.
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- 12. The DRAM of claim 12, wherein the gate insulation layer comprises a second high-k material layer with a dielectric constant of more than 10.
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17. A semiconductor device, comprising:
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a buried channel array transistor (BCAT) formed within a substrate, the BCAT comprising, a gate electrode, a capping layer pattern over the gate electrode, and source/drain regions adjacent to sidewalls of the gate electrode; and a gate insulation layer interposed between the substrate and the gate electrode, at least one of the capping layer pattern and the gate insulation layer including a material having a dielectric constant of 10 or more.
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18. The semiconductor device of claim 21, wherein,
the capping layer pattern includes a lower layer including the material having the dielectric constant of 10 or more, and an upper layer including a material having a dielectric constant of 3 or less, and upper surfaces of the upper layer and of the source/drain regions are at the same height.
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19. The semiconductor device of 23, wherein the gate insulation layer is further interposed between the upper layer and the source/drain regions.
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20. The semiconductor device of claim 21, wherein the capping layer pattern and the gate insulation layer include the material having a dielectric constant of 10 or more.
Specification