SEMICONDUCTOR DEVICES AND DYNAMIC RANDOM ACCESS MEMORY DEVICES INCLUDING BURIED GATE PATTERN WITH HIGH-K CAPPING LAYER

• US 20110169066A1
• Filed: 12/02/2010
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: MOON, Joon-Seok, WOO, Dong-Soo, LEE, Jinwoo, PARK, Keeshik, KAHNG, Jaerok
• Granted Patent: US 8,610,191 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

Claims

1. A semiconductor device, comprising:

a substrate having a gate trench;

a buried gate electrode partially filling the gate trench;

a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material layer that directly contacts an upper surface of the buried gate electrode;

source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode; and

a gate insulation layer interposed between the gate trench and the buried gate electrode.

2. The semiconductor device of claim 1, further comprising:

a low-k material layer stacked over the first high-k material layer of the capping layer pattern.

3. The semiconductor device of claim 2, wherein the first high-k material layer has a dielectric constant of more than 10, and the low-k material layer has a dielectric constant of less than 3.

4. The semiconductor device of claim 1, further comprising:

a high concentration impurity layer in an upper region of the source/drain regions.

5. The semiconductor device of claim 1, wherein the gate insulation layer includes a second high-k material layer with a dielectric constant of more than 10.

6. The semiconductor device of claim 1, wherein,

the source/drain regions extend from the upper surface of the substrate, and

bottom surfaces of the source/drain regions are lower than the upper surface of the buried gate electrode.

7. The semiconductor device of claim 2, wherein the gate insulation layer is interposed between the low-k material layer and the source/drain regions.

8. The semiconductor device of claim 2, wherein the gate insulation layer comprises a second high-k material layer with a dielectric constant of more than 10 and is interposed between the first high-k material layer and the source/drain regions.

9. A dynamic random access memory (DRAM), comprising:

an impurity layer in a substrate;

a gate trench in the impurity layer and dividing the impurity layer into respectively separated source/drain regions;

a buried gate electrode partially filling the gate trench;

a capping layer pattern in the gate trench and over the buried gate electrode, the capping layer pattern including a first high-k material;

an interlayer insulation layer covering the capping layer pattern and the source/drain regions;

a storage electrode over the interlayer insulation layer and electrically connected to one of the source/drain regions.

12. The DRAM of claim 12, wherein the gate insulation layer comprises a second high-k material layer with a dielectric constant of more than 10.

10. The DRAM of claim 11, further comprising:

a gate insulation layer interposed between an inner wall of the gate trench and the buried gate electrode.

11. The DRAM of claim 12, wherein the gate insulation layer is interposed between the capping layer pattern and the source/drain regions.

13. The DRAM of claim 11, wherein,

the capping layer pattern comprises a bottom capping layer pattern and a top capping layer pattern, which are sequentially stacked, and

the bottom capping layer pattern has a dielectric constant greater than that of the top capping layer pattern.

14. The DRAM of claim 16, wherein,

the bottom capping layer includes a second high-k material with a dielectric constant of more than 10, and

the top capping layer pattern includes a low-k material with a dielectric constant of less than 3.

15. The DRAM of claim 11, wherein an interface between the capping layer pattern and the buried gate electrode is lower than upper surfaces of the source/drain regions and higher than lower surfaces of the source/drain regions.

16. The DRAM of claim 11, further comprising high concentration impurity layers in upper regions of the source/drain regions, wherein the high concentration impurity layers have a higher impurity concentration than the source/drain regions.

17. A semiconductor device, comprising:

a buried channel array transistor (BCAT) formed within a substrate, the BCAT comprising,

a gate electrode,

a capping layer pattern over the gate electrode, and

source/drain regions adjacent to sidewalls of the gate electrode; and

a gate insulation layer interposed between the substrate and the gate electrode, at least one of the capping layer pattern and the gate insulation layer including a material having a dielectric constant of 10 or more.

18. The semiconductor device of claim 21, wherein,

the capping layer pattern includes a lower layer including the material having the dielectric constant of 10 or more, and an upper layer including a material having a dielectric constant of 3 or less, and

upper surfaces of the upper layer and of the source/drain regions are at the same height.

19. The semiconductor device of 23, wherein the gate insulation layer is further interposed between the upper layer and the source/drain regions.

20. The semiconductor device of claim 21, wherein the capping layer pattern and the gate insulation layer include the material having a dielectric constant of 10 or more.