Method and Apparatus for Use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink
First Claim
1. An RF switch circuit for switching RF signals, comprising:
- a) an RF input port receiving an RF input signal;
b) an RF output port;
c) a switch transistor grouping having a first node coupled to the RF input port and a second node coupled to the RF output port, wherein the switch transistor grouping is controlled by a first switch control signal (C1); and
d) a shunt transistor grouping having a first node coupled to the RF input port and a second node coupled to ground, wherein the shunt transistor grouping is controlled by a second switch control signal (C1x), and wherein the shunt transistor grouping comprises one or more ACC MOSFETs;
wherein each ACC MOSFET includes a floating body and wherein the ACC MOSFET is biased to selectively operate in the accumulated charge regime, and wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in the accumulated charge regime; and
wherein the ACC MOSFET further includes an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET, and wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (VACS) is applied to the ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the ACS;
and wherein when the first switch control signal C1 is enabled, the switch transistor-grouping is enabled and the shunt transistor grouping is disabled thereby passing the RF input signal through to the RF output port, and wherein when the second switch control signal C1x is enabled, the shunt transistor grouping is enabled while the switch transistor grouping is disabled thereby shunting the RF input signal to ground.
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Abstract
A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
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Citations
54 Claims
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1. An RF switch circuit for switching RF signals, comprising:
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a) an RF input port receiving an RF input signal; b) an RF output port; c) a switch transistor grouping having a first node coupled to the RF input port and a second node coupled to the RF output port, wherein the switch transistor grouping is controlled by a first switch control signal (C1); and d) a shunt transistor grouping having a first node coupled to the RF input port and a second node coupled to ground, wherein the shunt transistor grouping is controlled by a second switch control signal (C1x), and wherein the shunt transistor grouping comprises one or more ACC MOSFETs;
wherein each ACC MOSFET includes a floating body and wherein the ACC MOSFET is biased to selectively operate in the accumulated charge regime, and wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in the accumulated charge regime; and
wherein the ACC MOSFET further includes an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET, and wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (VACS) is applied to the ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the ACS;and wherein when the first switch control signal C1 is enabled, the switch transistor-grouping is enabled and the shunt transistor grouping is disabled thereby passing the RF input signal through to the RF output port, and wherein when the second switch control signal C1x is enabled, the shunt transistor grouping is enabled while the switch transistor grouping is disabled thereby shunting the RF input signal to ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
wherein, when C1 is enabled, the first switch and first shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal RF1 through to the RF common port and shunting the second RF input signal RF2 to ground, and wherein when C1 is disabled and C1x is enabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal RF2 through to the RF common port and shunting the first RF input signal RF1 to ground, and wherein the switch and shunt transistor groupings comprise one or more ACC MOSFETs defined by claim 1.
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37. The RF switch of claim 36, wherein each of the ACC MOSFETs include an ACS terminal in electrical communication with their respective and associated ACSs, and wherein the ACS terminals of each of the ACC MOSFETs are controlled by a sinking mechanism, and wherein the sinking mechanism removes accumulated charge from the ACC MOSFET bodies when the ACC MOSFETs operate in the accumulated charge regime.
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38. The RF switch of claim 37, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the bodies of the ACC MOSFETs.
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39. The RF switch of claim 37, wherein the ACC MOSFETs inherent drain-to-source breakdown voltage (BVDSS) characteristics, and wherein the BVDSS characteristics of the ACC MOSFETs are improved by removing or otherwise reducing the accumulated charge from the MOSFET bodies.
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40. The RF switch of claim 37, wherein the RF switch exhibits small-signal performance characteristics including insertion loss, insertion phase (delay), and isolation, and wherein the small-signal performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies.
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41. The RF switch of claim 37, wherein the RF switch includes associated temperature performance characteristics, and wherein the temperature performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies, and wherein the RF switch also exhibits decreased sensitivity to Vdd and fabrication process variations.
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42. The RF switch of claim 36, wherein the RF switch comprises a single-pole, multi-throw switch.
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43. The RF switch of claim 36, wherein the RF switch comprises a multi-pole, single-throw switch.
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44. The RF switch of claim 36, wherein the RF switch comprises a multi-pole, multi-throw switch.
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45. The RF switch of claim 1, wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology.
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46. The RF switch of claim 1, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.
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47. The ACC MOSFET of claim 1, wherein the MOSFET comprises an enhancement mode PMOSFET device.
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48. The ACC MOSFET of claim 1, wherein the MOSFET comprises a depletion mode PMOSFET device.
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49. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-insulator technology.
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50. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated on a semiconductor-on-sapphire substrate.
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51. The ACC MOSFET of claim 49, wherein the semiconductor-on-insulator technology comprises silicon-germanium (SiGe) fabricated on an insulating substrate.
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52. The ACC MOSFET of claim 49, wherein the semiconductor-on-insulator technology comprises gallium arsenide (GaAs) fabricated on an insulating substrate.
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53. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-bonded wafer technology.
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54. The ACC MOSFET of claim 53, wherein the MOSFET is fabricated on direct silicon bond substrates by bonding and electrically attaching a film of single-crystal silicon onto a base insulating substrate.
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30. A method of controlling the linearity characteristics of a floating body MOSFET, wherein the floating body MOSFET includes an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET and adapted to remove or otherwise control accumulated charge that accumulates in the MOSFET body when the MOSFET is operated in a off-state (non-conducting state), comprising:
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a) configuring the floating body MOSFET to operate in a selected circuit; b) biasing the floating body MOSFET to operate in an accumulated charge regime; and c) removing or otherwise controlling the accumulated charge. - View Dependent Claims (31)
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Specification