High Speed Processing of Financial Information Using FPGA Devices

• US 20110179050A1
• Filed: 03/31/2011
• Published: 07/21/2011
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Exegy Incorporated
• Inventors: Parsons, Scott, Chamberlain, Roger D., Taylor, David E., Schuehler, David Vincent, Franklin, Mark A.
• Granted Patent: US 8,626,624 B2
• Time in Patent Office: Days
• US Class Current: 707/755
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) receive the financial market data messages, and (2) parse each received financial market data message into its constituent data fields.

Claims

1. An apparatus for processing financial market data messages, each financial market data message comprising a plurality of data fields, each data field having a data value, the apparatus comprising:

a reconfigurable logic device configured to (1) receive the financial market data messages, and (2) parse each received financial market data message into its constituent data fields.

2. The apparatus of claim 1 wherein each message has any of a plurality of different formats, the apparatus further comprising a memory configured to store a data dictionary that defines how financial market data messages in a plurality of formats are to be parsed, and wherein the reconfigurable logic device is further configured to (1) determine the format exhibited by each received message, and (2) parse each received message into its constituent data fields as defined for the determined format in the data dictionary.

3. The apparatus of claim 2 wherein the memory comprises a memory device that is external to the reconfigurable logic device.

4. The apparatus of claim 3 wherein the memory device comprises at least one selected from the group consisting of an SRAM device and an SDRAM device.

5. An apparatus for processing financial market data, the financial market data comprising a plurality of data fields, each data field having a data value, the apparatus comprising:

a reconfigurable logic device configured to generate a plurality of financial market data messages from a plurality of the data fields, each generated message having a specified format.

6. The apparatus of claim 5 wherein each generated message exhibits any of a plurality of different formats, the apparatus further comprising a memory configured to store a data dictionary that defines a plurality of formats for financial market data messages, and wherein the reconfigurable logic device is further configured to access the data dictionary to determine how each generated message should be formatted.

7. The apparatus of claim 6 wherein the memory comprises a memory device that is external to the reconfigurable logic device.

8. The apparatus of claim 7 wherein the memory device comprises at least one selected from the group consisting of an SRAM device and an SDRAM device.