Non-Volatile Memory Device For Concurrent And Pipelined Memory Operations
First Claim
1. A memory device, comprising:
- a memory storage space having a plurality of storage units, each unit representing a minimum amount of storage space that must be programmed together;
a write data register to hold data for use in programming of at least one of the units, in connection with a multiple cycle state change operation;
a sense amplifier unit to read data from any of the units;
an input/output (IO) interface; and
internal routing to(i) couple the sense amplifier unit with the write data register, to feed back unit contents for use in the multiple cycle state change operation, and(ii) couple read data from one of the units to the IO interface, contemporaneous with the multiple cycle state change operation.
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Abstract
This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.
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Citations
43 Claims
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1. A memory device, comprising:
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a memory storage space having a plurality of storage units, each unit representing a minimum amount of storage space that must be programmed together; a write data register to hold data for use in programming of at least one of the units, in connection with a multiple cycle state change operation; a sense amplifier unit to read data from any of the units; an input/output (IO) interface; and internal routing to (i) couple the sense amplifier unit with the write data register, to feed back unit contents for use in the multiple cycle state change operation, and (ii) couple read data from one of the units to the IO interface, contemporaneous with the multiple cycle state change operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory device, comprising:
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a plurality of units of storage area; a sense mechanism to read data values from any of the units; a register to be used in programming data values into any of the units; a plurality of buffers; a crossbar coupling (i) each of the plurality of buffers with (ii) a selective one of either the write data register or the sense mechanism; and an input/output (IO) interface adapted to operatively couple each of the plurality of buffers with an external bus. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A memory device, comprising:
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means for tracking usage of each one of multiple buffers within the device; means for, in connection with a first memory operation, identifying a first one of the buffers as not currently being used, and for responsively loading first data associated with at least a page of memory in the device into the first one of the buffers; means for, in connection with a second memory operation, identifying a second one of the buffers as not currently being used, and for responsively loading second data associated with at least a page of memory in the device into the second one of the buffers; means for concurrently performing the first memory operation and the loading of the second data; and means for, responsive to the tracking, performing the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions.
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28. A method of operating a memory device, comprising:
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tracking usage of each one of multiple buffers within the device; in connection with a first memory operation, identifying a first one of the buffers as not currently being used and responsively loading first data associated with at least a page of memory in the device into the first one of the buffers; in connection with a second memory operation, identifying a second one of the buffers as not currently being used and responsively loading second data associated with at least a page of memory in the device into the second one of the buffers; concurrently performing the first memory operation and the loading of the second data; and responsive to the tracking, performing the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions. - View Dependent Claims (29, 30, 31, 32, 33)
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34. An apparatus comprising instructions stored on machine readable storage media, the apparatus being adapted for use in the control of at least one memory device having multiple buffers that are each used to hold data during memory operations, the at least one memory device adapted to concurrently perform each of a first memory operation and a second memory operation using different ones of the multiple buffers, the instructions when executed adapted to cause a machine to:
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track usage of each one of multiple buffers resident within the memory device; identify, in connection with the first memory operation, a first one of the buffers as not currently being used, and to responsively load first data associated with at least a page of memory in the device into the first one of the buffers; identify, in connection with the second memory operation, a second one of the buffers as not currently being used, and to responsively load second data associated with at least a page of memory in the device into the second one of the buffers; and responsive to the tracking, perform the identifying of the first one of the buffers and the identifying of the second one of the buffers on a dynamic basis, such that any one of the multiple buffers may be used for either the first memory operation or the second memory operation depending upon availability relative to prior transactions. - View Dependent Claims (35)
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36. For use with a memory storage array serviced by a plurality of buffers, each buffer coupled to an interface with a system data bus, an apparatus comprising:
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a state machine to track utilization of each one of the plurality of buffers; and a controller-resident command generator, the command generator coupled to the state machine, the command generator to generate buffer-specific commands in response to state machine contents. - View Dependent Claims (37, 38, 39, 40)
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41. A memory device, comprising:
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a memory storage space having a plurality of storage units, each storage unit representing a minimum amount of storage space that must be programmed together; a write data register to hold data for use in programming of at least one of the storage units, in connection with a multiple cycle state change operation, where the data in the write data register is changed during the multiple cycle state change operation; a buffer to hold a copy of the data loaded into the write data register, and in which the data is not changed during the multiple cycle state change operation; and control logic to serve a read request for the data undergoing programming in the at least one of the storage units from the buffer during the multiple cycle state change operation. - View Dependent Claims (42, 43)
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Specification