NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction;
word lines respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and
a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.
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Accused Products
Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.
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Citations
20 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction; word lines respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory system comprising:
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a nonvolatile semiconductor memory comprising a memory cell array and word lines, the memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction, the word lines being respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and a host controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A memory system comprising:
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a nonvolatile semiconductor memory comprising a memory cell array and word lines, the memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction, the word lines being respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and a host controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and perform a process (B) of moving data of the fail block to another block. - View Dependent Claims (17, 18, 19, 20)
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Specification