NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

• US 20110216592A1
• Filed: 03/03/2011
• Published: 09/08/2011
• Est. Priority Date: 03/03/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAGASHIMA, Hiroyuki
• Granted Patent: US 8,891,304 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction;

word lines respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and

a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.

2. The device of claim 1, further comprising a word line circuit configured to apply one of the first and second read voltages to the word lines.

3. The device of claim 1, further comprising:

bit lines connected to one-side ends of the NAND strings via select transistors; and

a bit line circuit connected to the bit lines and configured to determine pass/fail in the verify time.

4. The device of claim 1, wherein the controller writes a pass/fail result by the verifying process as a flag in a redundant area of the block.

5. The device of claim 4, wherein the controller confirms the flag in the data read time.

6. The device of claim 1, further comprising a latch circuit configured to store a pass/fail result by the verifying process as a flag.

7. The device of claim 6, wherein the controller confirms the flag in the data read time.

8. The device of claim 1, wherein the controller counts the number of NAND strings in which over-programming has occurred and performs the process (B) with respect to a block in which the count value exceeds a threshold value.

9. A memory system comprising:

a nonvolatile semiconductor memory comprising a memory cell array and word lines, the memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction, the word lines being respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and

a host controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.

10. The system of claim 9, wherein the nonvolatile semiconductor memory outputs a pass/fail result by the verify process to the host controller.

11. The system of claim 9, wherein the host controller receives a pass/fail result by the verify process from the nonvolatile semiconductor memory to form a table including the pass/fail result.

12. The system of claim 11, wherein the host controller confirms the table in the data read time.

13. The system of claim 11, wherein the host controller writes the table in the memory cell array.

14. The system of claim 9, wherein the nonvolatile semiconductor memory comprises a word line circuit that applies one of the first and second read voltages to the word lines.

15. The system of claim 9, wherein the nonvolatile semiconductor memory comprises bit lines connected to one-side ends of the NAND strings via select transistors, and a bit line circuit connected to the bit lines and configured to determine pass/fail in the verify time.

16. A memory system comprising:

a nonvolatile semiconductor memory comprising a memory cell array and word lines, the memory cell array comprising blocks that each comprise electrically rewritable memory cells, each of the blocks comprising NAND strings that each comprise a preset number of memory cells serially connected in a first direction, the word lines being respectively connected to memory cell groups arranged in a second direction that intersects with the first direction in the block; and

a host controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and perform a process (B) of moving data of the fail block to another block.

17. The system of claim 16, further comprising a correction circuit configured to correct an error in data of the fail block.

18. The system of claim 16, wherein the nonvolatile semiconductor memory outputs a pass/fail result by the verify process to the host controller.

19. The system of claim 16, wherein the host controller receives a pass/fail result by the verify process from the nonvolatile semiconductor memory to form a table including the pass/fail result.

20. The system of claim 19, wherein the host controller confirms the table in a data write time and inhibits the block in which over-programming has occurred from being used.