METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS
First Claim
1. A signal delay measurement circuit, comprising:
- an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal;
an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal;
an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and
a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal.
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Abstract
Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
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Citations
20 Claims
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1. A signal delay measurement circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal; an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A delay element calibration circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein a period of the test clock signal is adjustable; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with the test clock signal; and a chain of delay elements connected between the input register and the output register, the chain of delay elements defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method for minimizing skew between two signals, comprising:
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calibrating a coarse delay element; calibrating a fine delay element; measuring signal delay associated with a first signal using the calibrated coarse and fine delay elements; measuring signal delay associated with a second signal using the calibrated coarse and fine delay elements; determining a skew between the first and second signals as a difference between the measured signal delay associated with the first signal and the measured signal delay associated with the second signal; determining settings for coarse and fine delay modules to minimize the determined skew between the first and second signals, wherein the coarse and fine delay modules implement a selectable number of the coarse and fine delay elements respectively; and storing the determined settings for the coarse and fine delay modules in non-volatile memory. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification