Method and apparatus for minimizing skew between signals

• US 8,779,754 B2
• Filed: 02/01/2011
• Issued: 07/15/2014
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chong, Yan, Huang, Joseph, Sung, Chiakang, Chang, Eric Choong-Yin, Boyle, Peter, Wright, Adam J.
• Primary Examiner(s): NATALINI, JEFF WILLIAM
• Application Number:
  US13/019,277
• Publication Number:
  US 20110221497A1
• Time in Patent Office: 1,260 Days
• Field of Search: 324/76.54
• US Class Current: 324/76.54
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03K 5/1504 using a chain of active delay devices H03K5/15053 takes precedence

Abstract

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Claims

1. A signal delay measurement circuit, comprising:

an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein the test clock signal is a clock input to the input register;

an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register;

an emulation module connected between an output of the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the output register as the delayed version of the test data signal; and

a delay chain defined to introduce a selectable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal.

2. A signal delay measurement circuit as recited in claim 1, wherein each of the input and output registers is defined as a flip-flop.

3. A signal delay measurement circuit as recited in claim 1, wherein the actual signal transmission path for which the emulation module is defined is either a data signal path of a memory controller interface or a data strobe signal path of the memory controller interface.

4. A signal delay measurement circuit as recited in claim 1, wherein a total amount of signal delay to be introduced by the delay chain represents a signal delay between arrival of the test clock signal at the input register and arrival of the delayed version of the test clock signal at the output register.

5. A signal delay measurement circuit as recited in claim 1, wherein the delay chain includes a number of serially connected delay elements, an output node of each serially connected delay element connected to a respective input of a multiplexer, the multiplexer defined to pass through one of its inputs as the delayed version of the test clock signal in accordance with a delay select signal.

6. A signal delay measurement circuit as recited in claim 5, wherein the delay select signal is controllable such that the delayed version of the test clock signal can be set to correspond to a signal present at the output node of a particular delay element within the delay chain.

7. A signal delay measurement circuit as recited in claim 5, wherein the serially connected delay elements include a first coarse delay element followed by a number of fine delay elements.

8. A signal delay measurement circuit as recited in claim 1, wherein the signal delay measurement circuit is configured as a fine delay element calibration circuit having the emulation module defined as a coarse delay element and the delay chain defined to include a number of serially connected fine delay elements, an output node of each serially connected fine delay element connected to a respective input of a multiplexer, the multiplexer defined to pass through one of its inputs as the delayed version of the test clock signal in accordance with a delay select signal.

9. A delay element calibration circuit, comprising:

an input register defined to receive a test data signal and output the test data signal from an output of the input register in accordance with a test clock signal, wherein a period of the test clock signal is adjustable, and wherein the test clock signal is a clock input to the input register;

an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register;

a first delay element connected between the output of the input register and an input of the output register, the first delay element defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the input of the output register as the delayed version of the test data signal; and

a chain of selectable second delay elements connected between the clock input to the input register and the clock input to the output register, wherein the chain of selectable second delay elements generates the delayed test clock signal, and wherein the delayed test clock signal has a selectable delay governed by the chain of selectable second delay elements.

10. A delay element calibration circuit as recited in claim 9, wherein each of the input and output registers is defined as a flip-flop.

11. A delay element calibration circuit as recited in claim 9, wherein a total amount of signal delay to be introduced by the first delay element represents a total amount of signal delay of a coarse delay element, which can be applied in the delay element calibration circuit to calibrate the selectable second delay elements as fine delay elements.

12. A delay element calibration circuit as recited in claim 9, wherein the chain of selectable second delay elements is defined to provide a total signal delay that is larger than the signal delay of the first delay element.

13. A delay element calibration circuit as recited in claim 9, wherein the chain of selectable second delay elements includes a number of serially connected delay elements, each of the number of serially connected delay elements defined to provide a substantially equivalent amount of signal delay.

14. A delay element calibration circuit as recited in claim 9, further comprising:

a phase lock loop circuit defined to generate the test clock signal, the phase lock loop circuit defined to enable discrete adjustment of the period of the test clock signal.

15. A delay element calibration circuit, comprising:

a first input register defined to receive a first test data signal and output the first test data signal in accordance with a first test clock signal;

a first output register defined to receive a delayed version of the first test data signal and output the delayed version of the first test data signal in accordance with a delayed version of the first test clock signal;

a first delay module, connected between the first input register and the first output register and defined to provide the delayed version of the first test data signal;

a first delay chain defined to receive the first test clock signal and to provide the delayed version of the first test clock signal;

a second input register defined to receive a second test data signal and to output the second test data signal in accordance with a second test clock signal;

a second output register defined to receive a delayed version of the second test data signal and to output the delayed version of the second test data signal in accordance with the second test clock signal; and

a second delay chain connected between the second input register and the second output register and defined to provide the delayed version of the second test data signal;

wherein the second delay chain, the second input register and the second output register are configured to act as a calibration circuit for the first delay module or of the first delay chain.

16. The delay element calibration circuit of claim 15, wherein:

the first delay module includes a path emulation module;

the first delay chain includes a coarse delay element and a serially connected plurality of fine delay elements;

the second delay chain includes a serially connected plurality of coarse delay elements;

the first input register, the first output register and the first delay module are configured to measure a delay of the path emulation module; and

the second input register, the second output register and the second delay chain are configured to calibrate the coarse delay element of the first delay chain.

17. The delay element calibration circuit of claim 15, wherein:

the first delay module includes a coarse delay element;

the first delay chain includes a serially connected plurality of fine delay elements;

the second delay chain includes a serially connected plurality of coarse delay elements;

the second input register, the second output register and the second delay chain are configured to calibrate the coarse delay element of the first delay module; and

the first input register, the first output register and the first delay module are configured to measure a delay of the serially connected plurality of fine delay elements.

18. The delay element calibration circuit of claim 15, wherein:

the first delay module emulates a signal delay from a data strobe signal port to a clock port of an I/O flip-flop.

19. The delay element calibration circuit of claim 15, wherein:

the first delay chain includes a fine delay element;

the second delay chain includes a serially connected plurality of fine delay elements; and

the second input register, the second output register and the second delay chain are configured to calibrate the fine delay element of the first delay chain.

20. The delay element calibration circuit of claim 15, wherein:

the first delay chain includes a first multiplexer defined to transmit the delayed version of the first test clock signal to the first output register; and

the second delay chain includes a second multiplexer defined to transmit the delayed version of the second test data signal to the second output register.