METHOD OF FORMING SEMICONDUCTOR PATTERNS

• US 20110256727A1
• Filed: 04/13/2011
• Published: 10/20/2011
• Est. Priority Date: 04/14/2010
• Status: Active Grant

• Current Assignee: ASM Korea Ltd. (ASM International NV)
• Original Assignee: Asm Genitech Korea Ltd. (ASM International NV)
• Inventors: Inoue, Naoki, Beynet, Julien, Park, Hyung Sang
• Granted Patent: US 8,252,691 B2
• Time in Patent Office: Days
• US Class Current: 438/703
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.

Claims

1. A method of forming semiconductor patterns, the method comprising:

forming a photo resist template having a pattern of lines on a bottom layer, the pattern having a line width and a line spacing, the ratio of the line width to the line spacing being 1;

A wherein 1≦

A<

3;

depositing a spacer oxide conformal over the photo resist template by a Plasma Enhanced Atomic Layer deposition process, using sequential and alternating pulses of a silicon precursor and an oxygen plasma, such that trimming of the photo resist template occurs and the ratio of the line width to the line spacing becomes 1;

3 and the thickness of the deposited spacer oxide is about equal to the trimmed line width;

etching back the deposited spacer oxide such that spacer oxide films on upper and bottom surfaces of the pattern are removed, with spacer oxide films on side wall surfaces of the photo resist template remaining;

removing the photo resist template remaining between the spacer oxide films by selective etching; and

patterning the bottom layer by using the remaining spacer oxide films formed as mask.

2. The method of claim 1, further comprising:

trimming, prior to the step of depositing the spacer oxide, the photo resist pattern of lines such that the ratio of the line width to the line spacing becomes 1;

B, wherein A<

B<

3 by exposing the photo resist pattern of lines to pulses of the oxygen plasma, in the same reaction chamber in which the spacer oxide deposition is performed.

3. The method of claim 2, further comprising:

a PR footing reduction step prior to the step of depositing the spacer oxide, in the same reaction chamber in which PR trimming step and the spacer oxide deposition step are performed, the PR footing reduction step comprising a direct plasma exposure step.

4. The method of claim 3, wherein the PR footing reduction step is performed prior to the PR trimming step.

5. The method of claim 3, wherein the PR footing reduction step is performed after the PR trimming step.

6. The method of claim 1, wherein the plasma is a direct plasma.

7. The method of claim 1, wherein the plasma is a remote plasma.

8. The method of claim 2, wherein the plasma is a direct plasma.

9. The method of claim 2, wherein the plasma is a remote plasma.

10. The method of claim 1, wherein the silicon precursor is SiH2[N(C2H5)2]2.