Precise Resistor on a Semiconductor Device

• US 20110266637A1
• Filed: 04/29/2010
• Published: 11/03/2011
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Matt, Lee, Da-Yuan
• Granted Patent: US 8,361,848 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.

Claims

1. A method of making an integrated circuit, the method comprising:

forming a polysilicon layer on a substrate;

patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate;

performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor;

performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and

performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.

2. The method of claim 1, further comprising forming a high-k dielectric material layer on the substrate.

3. The method of claim 1, wherein the performing a second ion implantation includes implanting the polysilicon resistor using one of boron (B) and boron fluoride (BF2).

4. The method of claim 1, wherein the performing a first ion implantation includes implanting the polysilicon resistor using one of BF2 and B.

5. The method of claim 1, wherein the performing a second ion implantation includes implanting doping species to the top portion having a thickness less than about 5 nm.

6. The method of claim 5, wherein the top portion of the polysilicon resistor includes boron as dopant with a doping concentration greater than about 10¹⁹/cm³.

7. The method of claim 1, further comprising:

forming source and drain in the substrate and interposed by the polysilicon gate;

forming a metal layer in a gate trench formed after the performing an etch process;

filling the gate trench with a conductive layer on the metal layer; and

performing a chemical mechanical polishing process to remove excessive portions of the metal layer and the conductive layer.

8. The method of claim 7, wherein the source and drain are n-type dopant, and the metal layer has a work function less than 4.2 eV.

9. The method of claim 7, wherein the source and drain are p-type dopant, the metal layer has a work function greater than 5.2 eV.

10. The method of claim 1, wherein the performing a first ion implantation to the polysilicon layer includes performing the first ion implantation to the polysilicon layer before the patterning the polysilicon layer.

11. The method of claim 1, further comprising, after the performing a second ion implantation and before the performing an etch process:

forming an inter-level dielectric (ILD) layer on the semiconductor substrate; and

performing a first chemical mechanical polishing process to etch back the ILD layer.

12. An integrated circuit, comprising:

a semiconductor substrate;

a field-effect transistor (FET) disposed in a first region of the semiconductor substrate, the FET including a gate stack having a high k dielectric material layer, a metal layer having a proper work function and disposed on the high k dielectric material layer, and a conductive layer on the metal layer; and

a passive polysilicon device disposed in a second region of the semiconductor substrate, the passive polysilicon device including;

a polysilicon column feature having a boron-containing dopant of a first doping concentration; and

a top polysilicon portion disposed on the polysilicon column feature, wherein the top polysilicon portion includes the boron-containing dopant of a second doping concentration greater than the first doping concentration, and a thickness less than about 5 nm.

13. The integrated circuit of claim 12, wherein the first doping concentration is less than about 5×

10¹⁸/cm³.

14. The integrated circuit of claim 12, wherein the second doping concentration is greater than about 10¹⁹/cm³.

15. The integrated circuit of claim 12, wherein the second doping concentration ranging between about 10¹⁹/cm³ and about 10²²/cm³.

16. The integrated circuit of claim 12, wherein the FET further includes source and drain in the semiconductor substrate, the source and drain being of n-type dopant, and the work function of the metal layer is less than about 4.2 eV.

17. The integrated circuit of claim 12, wherein the FET further includes source and drain in the semiconductor substrate, the source and drain being of p-type dopant, and the work function of the metal layer is greater than about 5.2 eV.

18. The integrated circuit of claim 12, wherein the top polysilicon portion further includes fluorine dopant.

19. An integrated circuit, comprising:

a semiconductor substrate; and

a passive polysilicon device on the semiconductor substrate, the passive polysilicon device having a step-wise doping profile as

a first doping concentration in a bottom polysilicon portion of the passive polysilicon device; and

a second doping concentration in a top polysilicon portion of the passive polysilicon device, wherein the top portion has a thickness less than about 5 nm and the second doping concentration is substantially greater than the first doping concentration.

20. The integrated circuit of claim 19, further comprising

a field-effect transistor (FET) disposed in a first region of the semiconductor substrate, the FET including a gate stack having a high k dielectric material layer, a metal layer having a proper work function and disposed on the high k dielectric material layer, and a conductive layer on the metal layer;

and

the passive polysilicon device disposed in a second region of the semiconductor substrate, the passive polysilicon device including;

the bottom polysilicon portion having a boron-containing dopant of the first doping concentration; and

the top polysilicon portion on the polysilicon column feature, wherein the top polysilicon portion includes the boron-containing dopant of the second doping concentration.