Precise Resistor on a Semiconductor Device
First Claim
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1. A method of making an integrated circuit, the method comprising:
- forming a polysilicon layer on a substrate;
patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate;
performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor;
performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and
performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.
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Abstract
A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.
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Citations
20 Claims
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1. A method of making an integrated circuit, the method comprising:
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forming a polysilicon layer on a substrate; patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate; performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor; performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit, comprising:
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a semiconductor substrate; a field-effect transistor (FET) disposed in a first region of the semiconductor substrate, the FET including a gate stack having a high k dielectric material layer, a metal layer having a proper work function and disposed on the high k dielectric material layer, and a conductive layer on the metal layer; and a passive polysilicon device disposed in a second region of the semiconductor substrate, the passive polysilicon device including; a polysilicon column feature having a boron-containing dopant of a first doping concentration; and a top polysilicon portion disposed on the polysilicon column feature, wherein the top polysilicon portion includes the boron-containing dopant of a second doping concentration greater than the first doping concentration, and a thickness less than about 5 nm. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. An integrated circuit, comprising:
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a semiconductor substrate; and a passive polysilicon device on the semiconductor substrate, the passive polysilicon device having a step-wise doping profile as a first doping concentration in a bottom polysilicon portion of the passive polysilicon device; and a second doping concentration in a top polysilicon portion of the passive polysilicon device, wherein the top portion has a thickness less than about 5 nm and the second doping concentration is substantially greater than the first doping concentration. - View Dependent Claims (20)
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Specification