LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
First Claim
1. A method manufacturing a semiconductor structure comprising:
- forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;
forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;
forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion; and
forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion.
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Accused Products
Abstract
A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
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Citations
20 Claims
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1. A method manufacturing a semiconductor structure comprising:
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forming a gate dielectric and a gate electrode material layer on a semiconductor substrate; forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer; forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion; and forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor structure comprising:
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a first conductivity type well having a doping of a first conductivity type and located in a semiconductor substrate; a drift region having a doping of a second conductivity type which is the opposite of said first conductivity type, and located in said semiconductor substrate; a gate dielectric vertically abutting said first conductivity type well and said drift region; a gate electrode vertically abutting said gate dielectric and straddling over said first conductivity type well and said drift region; and a dielectric gate spacer of unitary construction and including two holes, wherein a first hole is filled by said gate electrode, and wherein a second hole is filled with a dielectric material. - View Dependent Claims (9, 10, 11)
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12. A method manufacturing a semiconductor structure comprising:
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forming a gate dielectric and a gate electrode on a semiconductor substrate; forming a first gate spacer on sidewalls of said gate electrode; forming a second gate spacer laterally surrounding said first gate spacer on said first gate spacer; forming a substrate contact semiconductor region in said semiconductor substrate on a source side of said gate electrode; removing a first portion of said second gate spacer on said source side of said gate electrode after forming said substrate contact semiconductor region; simultaneously forming a source region and a drain region after removal of said first portion of said second gate spacer, wherein said source region is formed in said semiconductor substrate on said source side of said gate electrode and said drain region is formed in said semiconductor substrate on a drain side of said gate electrode, wherein a first lateral distance between said substrate contact semiconductor region and said gate electrode is the same as a second lateral distance between said drain region and said gate electrode; and removing a second portion of said second gate spacer on said drain side of said gate electrode after formation of said drain region. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification