Apparatus and Method for Processing Wirelessly Communicated Data and Clock Information Within an Electronic Device
1 Assignment
0 Petitions
Accused Products
Abstract
An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14) may include a first processor (18) that controls only wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12), a second processor (16) that controls the operations associated only with the electronic device (12) and excluding the wireless communications with the another device (14), and means (30-30″″) for extracting the clock information and the data from the wirelessly received information and providing a corresponding clock signal and the data to the second processor (16) for synchronous receipt of the data by the second processor (16) using the clock signal.
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Citations
21 Claims
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1-10. -10. (canceled)
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11. An electronic device for processing information wirelessly received from another electronic device, the wirelessly received information including embedded data and clock information, the electronic device comprising:
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a first processor configured to extract at least one information packet containing the embedded data and clock information from the information wirelessly received by the electronic device from the another electronic device and to produce the at least one information packet at an output thereof, a clock and data decoding circuit having an input connected to the output of the first processor and an output, the clock and decoding circuit configured to extract the clock information from the at least one information packet, to fully decode the data from the at least one information packet, and to produce the fully decoded data and a clock signal corresponding to the extracted clock information at the output thereof, and a second processor having an input connected to the output of the clock and data decoding circuit, the second processor configured to synchronously read the fully decoded data received from the clock and data decoding circuit using the clock signal received from the clock and data decoding circuit, and to thereafter processes the fully decoded data. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification