MEMORY DEVICE AND SIGNAL PROCESSING CIRCUIT

• US 20120294068A1
• Filed: 05/17/2012
• Published: 11/22/2012
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ishizu, Takahiko
• Granted Patent: US 8,964,450 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/10 for interconnecting capacitors

Abstract

A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a second node, a third node, and a fourth node; a first control circuit connected to the first node, the second node, and the third node; a second control circuit connected to the first node, the second node, and the fourth node; a first memory circuit connected to the first node, the first control circuit, and the second control circuit; and a second memory circuit connected to the second node, the first control circuit, and the second control circuit.

Claims

1. A semiconductor device comprising:

a memory circuit comprising a first transistor and a capacitor;

a logic circuit comprising a second transistor, a third transistor, a fourth transistor, and a fifth transistor; and

a control circuit comprising a sixth transistor,

wherein a first terminal of the first transistor is electrically connected to one electrode of the capacitor,

wherein a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor, a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the sixth transistor,

wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the sixth transistor,

wherein a second terminal of the third transistor is electrically connected to a first terminal of the fifth transistor, and

wherein a gate of the second transistor and a gate of the third transistor are electrically connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor.

2. The semiconductor device according to claim 1, wherein the first transistor comprises an oxide semiconductor.

3. The semiconductor device according to claim 2, wherein the oxide semiconductor comprises two or more elements selected from indium, gallium, tin, and zinc.

4. The semiconductor device according to claim 1, further comprising a precharge circuit,

wherein a first terminal of the precharge circuit is electrically connected to the first terminal of the first transistor, the first terminal of the second transistor, the first terminal of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the sixth transistor, and

wherein a second terminal of the precharge circuit is electrically connected to the gate of the second transistor, the gate of the third transistor, the second terminal of the fourth transistor, and the second terminal of the fifth transistor.

5. The semiconductor device according to claim 1, wherein each of the third transistor and the fifth transistor is a p-channel transistor.

6. The semiconductor device according to claim 1, wherein a plurality of the semiconductor devices are arranged in matrix.

7. A semiconductor device comprising:

a switch configured to output a data signal to a logic circuit in response to a control signal;

the logic circuit configured to hold the data signal in a period during which a first power supply voltage is supplied;

a control circuit configured to output a second power supply potential to the logic circuit in accordance with the data signal; and

a nonvolatile memory circuit configured to hold the data signal in response to a second control signal,

wherein the nonvolatile memory circuit is configured to hold the data signal during the supply of the first power supply voltage is stopped.

8. The semiconductor device according to claim 7,

wherein the nonvolatile memory circuit comprises a transistor and a capacitor, and

wherein the transistor comprises an oxide semiconductor.

9. The semiconductor device according to claim 8, wherein the oxide semiconductor comprises two or more elements selected from indium, gallium, tin, and zinc.

10. The semiconductor device according to claim 7, further comprising a precharge circuit configured to supply a precharge potential to the logic circuit.

11. The semiconductor device according to claim 7, wherein the logic circuit comprises an inverter circuit.

12. The semiconductor device according to claim 7, wherein a plurality of the semiconductor devices are arranged in matrix.