Circuit Arrangement with an Adjustable Transistor Component

• US 20120306464A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: HIRLER, Franz, FELDTKELLER, Martin, DEBOY, Gerald
• Granted Patent: US 9,166,028 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

Disclosed is a circuit arrangement, including a transistor component with a gate terminal, a control terminal, and a load path between a source and a drain terminal, and a drive circuit connected to the control terminal and configured to determine a load condition of the transistor component, to provide a drive potential to the control terminal, and to adjust the drive potential dependent on the load condition.

Claims

1. A circuit arrangement, comprising:

a transistor arrangement comprising a plurality of n transistors, with n≧

2, each comprising a gate terminal, and a load path between a source and a drain terminal, and m, with m≦

n and m≧

1 of the n transistors comprising a control terminal wherein the control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement; and

a drive circuit configured to adjust the activation state of the m transistors comprising a control terminal independent of the others of the plurality of transistors to one of a first and second activation state, to determine a load condition of the transistor arrangement, and to select k, with k≧

0, transistors that are driven to assume the first activation state and m−

k transistors that are driven to assume the second activation state dependent on the load condition.

2. The circuit arrangement of claim 1, wherein each of the transistors has an active area, the individual transistors have identical sizes of their active area, and the number k is dependent on the load condition.

3. The circuit arrangement of claim 1, wherein each of the transistors has an active area, at least some of the n transistors have different sized active areas, and the drive circuit is configured to select the k transistors that are in the first activation state such that a sum of the sizes of the active areas of the transistors in the first activation state is dependent on the load condition.

4. The circuit arrangement of claim 1, wherein each of the transistor devices has an output capacitance value and is configured to have a voltage dependency of this output capacitance value varied by the corresponding control signal.

5. The circuit arrangement of claim 4, wherein each of the transistor devices has an on-resistance and is configured to have the on-resistance varied by the corresponding control signal.

6. The circuit arrangement of claim 5, wherein the control signal of each of the transistors is selected such that the on-resistance is lower in the first activation state than in the second activation state.

7. The circuit arrangement of claim 6, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and the drive circuit is configured to determine a current flowing through the load path of the transistor arrangement, and to select the k transistors driven in the first activation state dependent on the determined current.

8. The circuit arrangement of claim 2, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and k increases with increasing current.

9. The circuit arrangement of claim 3, wherein the load condition is dependent on a current flowing through the load path of the transistor arrangement, and the sum of the sizes of the active areas of the transistors in the first activation state increases with increasing current.

10. The circuit arrangement of claim 5, wherein the drive circuit is configured to determine a mean value or rms value of the current flowing through the load path of the transistor arrangement within a given time period, and to select the k transistors driven in the first activation state dependent on the determined mean or rms value.

11. The circuit arrangement of claim 1, wherein the drive circuit is further configured to provide at least one gate signal configured to switch the plurality of transistors on or off.

12. The circuit arrangement of claim 11, wherein the drive circuit is configured to drive the plurality of transistor to be switched on or to be switched off in common.

13. The circuit arrangement of claim 11, wherein the drive circuit is configured to permanently switch the n−

k transistors off.

14. The circuit arrangement of claim 1, the drive circuit is configured to cyclically switch on and off at least some of the plurality of transistors, the load condition is dependent on a switching frequency of cyclically switching on and off the transistors, and the drive circuit is configured to set the k transistors driven to assume the first activation state dependent on the switching frequency.

15. The circuit arrangement of claim 2, wherein the load condition is dependent on switching frequency at which the transistor arrangement is cyclically switched on and off, and k decreases with increasing switching frequency.

16. The circuit arrangement of claim 3, wherein the load condition is dependent on switching frequency at which the transistor arrangement is cyclically switched on and off, and the sum of the sizes of the active areas of the transistors in the first activation state decreases with increasing switching frequency.

17. The circuit arrangement of claim 1, wherein the plurality of transistors is implemented in one semiconductor body.

18. The circuit arrangement of claim 1, wherein the plurality of transistors is implemented in at least two semiconductor bodies, and each of the transistors is implemented in only one of the at least two semiconductor bodies.

19. The circuit arrangement of claim 1, wherein each of the n transistors has a control terminal and the drive circuit provides n drive signals.

20. A switching converter, comprising:

input terminals configured to apply an input voltage;

output terminals configured to provide an output voltage;

a rectifier-inductor arrangement coupled between the input terminals and the output terminals;

a control circuit configured to receive an output voltage signal that is dependent on the output voltage, to provide a drive signal, and to assume one of at least two different operation modes;

a transistor arrangement comprising a plurality of n transistors, with n≧

2, each comprising a gate terminal, and a load path between a source and a drain terminal, and at least m, with m≦

n and m≧

1 of the n transistors comprising a control terminal wherein the control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement; and

a drive circuit configured to adjust the activation state of the m transistors comprising a control terminal independent of the others of the plurality of transistors to one of a first and second activation state, to determine a load condition of the transistor arrangement, and to select k, with k≧

0, transistors that are driven to assume the first activation state and m−

k transistors that are driven to assume the second activation state dependent on the operation mode of the control circuit.

21. The switching converter of claim 20, wherein one of the operation modes is a burst mode, and one of the operation modes is a normal operation mode.

22. The switching converter of claim 21, wherein each of the transistors has an active area, the individual transistors have identical sizes of their active area, and the drive circuit is configured to drive a first number of transistors to assume the first activation when the control circuit is in the normal operation mode, and to drive a second number of transistors to assume the first activation state when the control circuit is in the burst mode, wherein the second number is lower than the first number.

23. The switching converter of claim 21, wherein the first number equals the number n of transistors of the transistor arrangement.

24. The switching converter of claim 22, wherein the second number is between 0.1 times n and 0.6 times n.

25. The switching converter of claim 20, wherein each of the transistors has an active area, at least some of the n transistors have different sizes of their active areas, and the drive circuit is configured to select the k transistors that are in the first activation state such that a sum of the sizes of the active areas of the transistors in the first activation state is lower when the control circuit is in the burst mode than in the normal operation mode.

26. The switching converter of claim 24, wherein in the normal operation mode, the sum of the sizes of the active areas of the transistors in the first activation state equals an overall size of the active areas of the n transistors.

27. The switching converter of claim 24, wherein in the burst mode, the sum of the sizes of the active areas of the transistors in the first activation state is between 0.1 times n and 0.6 times equals an overall size of the active areas of the n transistors.

28. The switching converter of claim 20, wherein the rectifier arrangement has one of a buck topology, a boost topology, a buck-boost topology, a flyback topology.