INTERCONNECTION SYSTEM

• US 20130042119A1
• Filed: 04/10/2012
• Published: 02/14/2013
• Est. Priority Date: 04/21/2005
• Status: Active Grant

• Current Assignee: Innovations In Memory LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: Bennett, Jon C.R.
• Granted Patent: US 9,582,449 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Claims

1. A memory module, comprising:

a read-write memory device; and

a configurable switching element (CSE), having a plurality of lanes for transmitting or receiving signals;

wherein the CSE is configurable to change a power state of a lane of the plurality of lanes at a future time, and to exchange data between a first lane and a second lane so as to alter a time delay difference between signals on the first lane and the second lane when the signals are received at another memory module.

2. The memory module according to claim 1, wherein the future time has a time value determined by a control signal.

3. The memory module according to claim 2, wherein the future time value associated with at least one of the plurality of lanes is individually specified.

4. The memory module according to claim 1, wherein the power state of at least one of the plurality of lanes is configurable.

5. The memory module of claim 1, wherein the power state of each of the plurality of lanes is one of powered up, or powered down.

6. The memory module of claim 1, wherein the power state of each of the plurality of lanes is one of powered up, powered down, or standby.

7. The memory module of claim 1, wherein the CSE is configurable such that a logical assignment of data received by the receiving signal lines and a logical assignment of data to be transmitted by the transmitting signal lines is alterable.

8. The memory module of claim 1, further comprising first, second and third ports, wherein the CSE is configurable such that a signal received on any of the first, the second or the third ports is transmittable on at least one of the lanes of the first, the second or the third ports.

9. The memory module of claim 8, wherein at least one of the lanes is reconfigurable as a receiving or a transmitting lane.

10. The memory module of claim 1, wherein a signal is transmitted on at least one of the lanes during a fixed time interval.

11. The memory module of claim 1, wherein the fixed time interval is determined such that at least one of data edge tracking, clock, clock phase, or frame synchronization is maintained.

12. A configurable switching element (CSE), comprising:

a plurality of lanes capable of at least one of receiving or transmitting data signals, wherein a first lane is configured to receive a first data signal; and

a second lane has a controllable power state,

wherein the CSE is configurable to exchange received data signals between a third lane and a fourth lane for transmission thereon, and to control the power state of the second lane at a time after the transmission of the data signals.

13. The CSE of claim 12, wherein the power state of the second lane is controlled to be one of powered on, powered off, or standby.

14. The CSE of claim 13, wherein one or more of the plurality of the lanes is reconfigurable as a receiving or a transmitting signal lane.

15. The CSE of claim 12, wherein the power state of a second lane is controlled to be one of powered on, or powered off.

16. The CSE of claim 12, wherein the first data signal received by the first lane controls the power state of the second lane.

17. The CSE of claim 12, wherein a signal received on the second lane is routed to another lane or a memory interface.

18. The CSE of claim 12, where the memory interface is connectable to a memory circuit.

19. The CSE of claim 18, wherein the memory circuit is a semiconductor circuit.

20. The CSE of claim 18, wherein in the memory circuit is fabricated as at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), or a flash memory (FLASH).

21. The CSE of claim 12, wherein the exchange of signals between the first and the second lanes is dependent on a differential time delay between a signal received on the first lane and a signal received on another pair of lanes.

22. A configurable switching element (CSE), comprising:

a first port and a second port for at least one of receiving or transmitting a signal, at least one port of the first port and the second port having a plurality of lanes,

wherein the CSE is configurable to perform at least two of;

change a power state of at least one of the plurality of lanes at a time after the transmission of a signal on at least another one of the plurality of lanes, route the signal to the second port, or exchange signals between pairs of lanes.

23. The CSE of claim 22, further comprising a memory interface.

24. The CSE of claim 22, wherein the CSE is configurable to route a received second signal to the second port.

25. The CSE of claim 22, wherein the power state of each of the plurality of lanes is one of powered up, powered down, or standby.

26. The CSE of claim 25, wherein the power state of each of the plurality of lanes is one of powered up, or powered down.

27. The CSE of claim 22, each of at least two of the lanes connectable to a signal line having either a transmitting end or a receiving end wherein the CSE is configurable such that logical data exchange of data on the receiving end of the signal lines and the transmitting end of the signal lines is performed.

28. The CSE of claim 22, having a third port, and configurable so that a signal received on any signal line of any of the first, the second or the third ports is transmitted on any of the plurality of lines connectable to the first, the second or the third ports.

29. The CSE of claim 22, wherein the exchange of signals between pairs of lanes is determined based on a differential time delay between signals received on another pair of lanes.

30. A computer program product including software stored on a computer readable medium, comprising:

instructions for configuring an apparatus including a processor and a port for at least one of receiving or transmitting signals, each port having a plurality of lanes and at least one lane of the plurality of lanes having a controllable power state; and

wherein a first signal received on one of the plurality of lanes is interpreted cause to at least one of;

a change to future-time power state of at least one lane of the plurality of lanes based on the received first signal or an exchange of second received between pairs of lanes of the plurality of lanes,

wherein the computer readable medium is any medium that is capable of storing instructions for execution by a computing machine or special-purpose hardware.