VERTICAL 4-WAY SHARED PIXEL IN A SINGLE COLUMN WITH INTERNAL RESET AND NO ROW SELECT

• US 20130128089A1
• Filed: 01/03/2013
• Published: 05/23/2013
• Est. Priority Date: 10/01/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yin, Zhiping, Fan, Xiaofeng, Li, Xiangli
• Granted Patent: US 9,210,347 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Claims

1-10. -10. (canceled)

11. A method of reading from a pixel circuit comprising a plurality of 4-way shared pixels in a column of a pixel array where each pixel circuit has a plurality of different colored pixels, said method comprising:

applying a logic high signal on a reset control line to turn on a reset transistor, the reset transistor, when turned on, causing a reset voltage to be applied on a column line;

applying a logic low signal on the reset control signal to turn off the reset transistor;

applying a logic high signal to enable readout of the column line;

reading out a pixel reset signal from the pixel circuit; and

reading out a pixel image signal from the pixel circuit.

12. The method of claim 11, wherein said step of reading out the pixel reset signal further comprises:

applying a logic high pulse on a sample and hold reset signal control line.

13. The method of claim 12, wherein said step of reading out the pixel reset signal further comprises:

applying a logic high pulse on a transfer control line after the step of applying a logic high pulse on the sample and hold reset signal control line.

14. The method of reading from a pixel circuit of claim 13, wherein said step of reading out the pixel image signal further comprises:

applying a logic high pulse on a sample and hold signal control line after the step of applying a logic high pulse on the transfer control line.

15-24. -24. (canceled)

25. A method of reading from a pixel circuit comprising a plurality of at least four pixels in a first column of a pixel array, each pixel including a photosensor and commonly electrically coupled to a storage region, said method comprising:

turning on a reset transistor common to all of the plurality of at least four pixels, causing a reset voltage to be applied on a column line of the first column;

turning off the reset transistor;

enabling the column line for readout;

reading out the reset voltage from the pixel circuit; and

reading out a pixel image signal from the pixel circuit.

26. The method of claim 25, further comprising using a sample and hold circuitry to sample and hold the reset voltage from the pixel circuit.

27. The method of claim 26, further comprising, after the reset voltage is read from the pixel circuit, transferring accumulated charge from the photosensors to the storage region.

28. The method of claim 27, further comprising using a sample and hold circuitry to sample and hold the accumulated charge from the photosensors.