ACTIVE NON-VOLATILE MEMORY POST-PROCESSING
First Claim
Patent Images
1. A computing node comprising:
- an active Non-Volatile Random Access Memory (NVRAM) component comprising;
memory to store data chunks received from a processor core, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and
a sub-processor component to perform post-processing of said data chunks based on said metadata.
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Abstract
A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.
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Citations
15 Claims
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1. A computing node comprising:
an active Non-Volatile Random Access Memory (NVRAM) component comprising; memory to store data chunks received from a processor core, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and a sub-processor component to perform post-processing of said data chunks based on said metadata. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for post-processing, the method comprising:
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with a computing node, storing data chunks received from a processor core into a memory of an active Non-Volatile Random Access Memory (NVRAM) component, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and with a sub-processor component of said active NVRAM component, performing post-processing of said data chunks based on said metadata. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computing system comprising:
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a number of computing nodes, each node comprising; an active Non-Volatile Random Access Memory (NVRAM) component comprising; memory to store Input/Output (I/O) data chunks received from a processor core, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and a sub-processor component to perform post-processing of said I/O data based on said metadata; and a global active queue to use a balanced tree data structure to distribute processing of said data chunks across said number of computing nodes according to an order identifier assigned to said data chunks.
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Specification