SOI SWITCH ENHANCEMENT
First Claim
1. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:
- a plurality of field effect transistor (FET) devices, wherein each FET device of the plurality of FET devices includes a gate contact, a drain contact, and a source contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled to a second end of the chain, and wherein the gate contact of the FET device at the second end of the chain is a first gate contact;
a plurality of gate biasing circuits coupled in series, wherein each one of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices, and further wherein each one of the plurality of gate biasing circuits includes a resistor; and
a plurality of gate speedup circuits, wherein each one of the plurality of gate speedup circuits is coupled across a corresponding gate biasing circuit of the plurality of gate biasing circuits.
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Accused Products
Abstract
The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.
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Citations
16 Claims
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1. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:
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a plurality of field effect transistor (FET) devices, wherein each FET device of the plurality of FET devices includes a gate contact, a drain contact, and a source contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled to a second end of the chain, and wherein the gate contact of the FET device at the second end of the chain is a first gate contact; a plurality of gate biasing circuits coupled in series, wherein each one of the plurality of gate biasing circuits is coupled between a corresponding pair of gate contacts of the plurality of FET devices, and further wherein each one of the plurality of gate biasing circuits includes a resistor; and a plurality of gate speedup circuits, wherein each one of the plurality of gate speedup circuits is coupled across a corresponding gate biasing circuit of the plurality of gate biasing circuits. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:
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a plurality of field effect transistor (FET) devices, wherein each FET device of the plurality of FET devices includes a gate contact, a drain contact, and a source contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled to a second end of the chain, and wherein the gate contact of the FET device at the second end of the chain is a first gate contact; a plurality of drain-source biasing circuits coupled in series, wherein each one of the plurality of drain-source biasing circuits is coupled between a corresponding drain contact and source contact of one of the plurality of FET devices, and further wherein each one of the plurality of drain-source biasing circuits includes a resistor; and a plurality of drain-source speedup circuits, wherein each one of the plurality of drain-source speedup circuits is coupled across a corresponding drain-source biasing circuit of the plurality of drain-source biasing circuits. - View Dependent Claims (8, 9, 10, 11)
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12. A serially stacked shunt semiconductor on insulator (SOI) switch comprising:
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a plurality of field effect transistor (FET) devices, wherein each FET device of the plurality of FET devices includes a gate contact, a drain contact, a source contact, and a body contact, and such that the plurality of FET devices are coupled in series to form a chain having a first drain at a first end of the chain, a first source coupled to a second end of the chain, and wherein the body contact of the FET device at the second end of the chain is a first body contact; a plurality of body biasing circuits coupled in series, wherein each one of the plurality of body biasing circuits is coupled between the body contact of a corresponding FET device and the body contact of an adjacent FET device, and further wherein each one of the plurality of body biasing circuits includes a resistor; and a plurality of body speedup circuits, wherein each one of the plurality of body speedup circuits is coupled across a corresponding body biasing circuit of the plurality of body biasing circuits. - View Dependent Claims (13, 14, 15, 16)
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Specification