System and Method for Testing an Integrated Circuit

• US 20130307576A1
• Filed: 05/16/2012
• Published: 11/21/2013
• Est. Priority Date: 05/16/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ilkov, Nikolay, Bakalski, Winfried
• Granted Patent: US 9,588,171 B2
• Time in Patent Office: Days
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28

Abstract

In accordance with an embodiment, a method of testing an integrated circuit, includes receiving a supply voltage on the integrated circuit via a first input pin, providing power to circuits disposed on the integrated circuit via the first input pin, comparing the supply voltage to an internally generated voltage, generating a digital output value based on the comparing, and applying the digital output value to a pin of the integrated circuit.

Claims

1. A method of testing an integrated circuit, the method comprising:

receiving a supply voltage on the integrated circuit via a first input pin;

providing power to circuits disposed on the integrated circuit via the first input pin;

comparing the supply voltage to an internally generated voltage;

generating a digital output value based on the comparing; and

applying the digital output value to a pin of the integrated circuit.

2. The method of claim 1, wherein comparing the supply voltage to the internally generated voltage comprises using a comparator.

3. The method of claim 1, wherein comparing the supply voltage to the internally generated voltage comprises using an analog-to digital converter.

4. The method of claim 1, wherein comparing the supply voltage to an internally generated voltage comprises dividing the supply voltage using a resistive voltage divider.

5. The method of claim 1, wherein applying the digital output value to the pin of the integrated circuit comprises transmitting the digital output value via a serial data interface.

6. The method of claim 1, wherein comparing the supply voltage to an internally generated voltage comprises comparing the supply voltage to a node of an internal voltage regulator.

7. The method of claim 6, wherein the node of the internal voltage regulator is a feedback voltage of the internal voltage regulator.

8. The method of claim 1, wherein comparing the supply voltage to an internally generated voltage comprises comparing the supply voltage to an output voltage of a charge pump.

9. The method of claim 8, wherein comparing the supply voltage to the output voltage of the charge pump comprises comparing a divided supply voltage with a divided charge pump output voltage.

10. The method of claim 1, further comprising producing the internally generated voltage based on an internal current.

11. The method of claim 10, wherein producing the internally generated voltage based on the internal current comprising converting a current between an output of an internal regulator circuit and a load of the internal regulator circuit into the internally generated voltage.

12. The method of claim 11, wherein the load of the internal regulator circuit comprises a charge pump.

13. A method of testing a MOS switch, the method comprising:

pumping a substrate of the MOS switch to a negative voltage;

comparing an output node of a MOS switch to a reference voltage; and

determining a failed test condition when the output node of the MOS switch is less than the reference voltage.

14. The method of claim 13, wherein the substrate of the MOS switch comprises a well disposed in a semiconductor substrate.

15. An integrated circuit comprising:

a first circuit;

a digital interface; and

a data converter having a first input coupled to a supply voltage, a second input coupled to the first circuit, and an output coupled to the digital interface, wherein the digital interface is readable in a test mode.

16. The integrated circuit of claim 15, wherein the data converter comprises a comparator.

17. The integrated circuit of claim 15, wherein the digital interface comprises a serial interface.

18. The integrated circuit of claim 15, wherein:

the first circuit comprises a voltage regulator;

the first input of the data converter is coupled to the supply voltage via a voltage divider; and

the second input of the data converter is coupled to a feedback voltage of the regulator.

19. The integrated circuit of claim 18, wherein the digital interface is configured to indicate an output state of the data converter in the test mode.

20. The integrated circuit of claim 15, wherein:

the first circuit comprises a voltage regulator;

the first input of the data converter is coupled to the supply voltage via a voltage divider;

the integrated circuit further comprises a current measuring circuit coupled in series with an output of the voltage regulator; and

the second input of the data converter is coupled to an output of the current measuring circuit.

21. The integrated circuit of claim 20, wherein the current measuring circuit comprises a differential amplifier having inputs coupled to a current measuring resistor.

22. The integrated circuit of claim 15, wherein:

the first circuit comprises a charge pump;

the first input of the data converter is coupled to the supply voltage via a first voltage divider; and

the second input of the data converter is coupled to an output of the charge pump.

23. The integrated circuit of claim 22, wherein the second input of the data converter is coupled to the output of the charge pump via a second voltage divider coupled between the supply voltage and the output of the charge pump.

24. The integrated circuit of claim 15, wherein:

the first circuit comprises a charge pump;

the first input of the data converter is coupled to the supply voltage via a first voltage divider;

the integrated circuit further comprises a current measuring circuit coupled in series with an output of the charge pump and a substrate connection of a semiconductor switch; and

the second input of the data converter is coupled to an output of the current measuring circuit.

25. An integrated circuit comprising:

a semiconductor switch;

a digital interface; and

a comparator having a first input coupled to a reference voltage, a second input coupled to a substrate connection of the semiconductor switch, and an output coupled to the digital interface.

26. The integrated circuit of claim 25, wherein the reference voltage is less than or equal to a ground voltage.

27. The integrated circuit of claim 25, wherein the digital interface is configured to indicate whether a first fault condition exists based on whether the comparator indicates that a voltage of the substrate connection is greater than the reference voltage.

28. The integrated circuit of claim 27, wherein the first fault condition comprises a substrate leakage condition.

29. An integrated switch system comprising:

a voltage regulator;

a digital interface;

a power supply input;

a charge pump;

an RF switch; and

a measurement interface circuit comprising a comparator having a first input coupled to the power supply input, a second input coupled to a parameter measurement node, and an output coupled to the digital interface.

30. The integrated switch system of claim 29, wherein the digital interface comprises a serial interface.

31. The integrated switch system of claim 29, wherein the RF switch comprises a plurality of RF switches.

32. The integrated switch system of claim 29, wherein:

wherein the first input of the comparator is coupled to the power supply input via a voltage divider; and

the second input of the comparator is coupled to a feedback node of the voltage regulator.

33. The integrated switch system of claim 29, wherein:

the first input of the comparator is coupled to the power supply input via a voltage divider;

the measurement interface circuit further comprises a current measurement circuit coupled in series with an output of the voltage regulator; and

the second input of the comparator is coupled to the current measurement circuit.

34. The integrated switch system of claim 33, wherein the current measurement circuit comprises:

a resistor coupled in series with an output of the voltage regulator; and

an amplifier having a positive input coupled to a first terminal of the resistor, a negative input coupled to a second terminal of the resistor and an output coupled to the second input of the comparator.

35. The integrated switch system of claim 29, wherein:

the first input of the comparator is coupled to the power supply input via a voltage divider; and

the measurement interface circuit further comprises a current measurement circuit coupled in series with an output of the charge pump and a substrate connection of the RF switch.

36. The integrated switch system of claim 29, wherein:

the first input of the comparator is coupled to the power supply input via a first voltage divider; and

the second input of the comparator is coupled to a second voltage divider coupled between an output of the charge pump of the power supply input.