VOLTAGE REGULATOR, VOLTAGE REGULATING SYSTEM, MEMORY CHIP, AND MEMORY DEVICE
First Claim
1. A voltage regulator comprising:
- a power source terminal configured to supply a power source voltage;
an output terminal configured to output a load current;
a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first current, and wherein the first transistor outputs the first current to the output terminal; and
a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second current different from the first current, and wherein the second transistor outputs the second current to the output terminal,wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.
1 Assignment
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Accused Products
Abstract
A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.
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Citations
35 Claims
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1. A voltage regulator comprising:
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a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first current, and wherein the first transistor outputs the first current to the output terminal; and a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second current different from the first current, and wherein the second transistor outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A voltage regulator comprising:
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a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which have a first terminal connected to the power source terminal, a second terminal connected to the output terminal, and a gate terminal connected to an amplifier; and a second transistor which have a first terminal connected to the power source terminal, a second terminal connected to the output terminal, and a gate terminal connected to one end of each of a first switch and a second switch, wherein the other end of the first switch is connected to the power source terminal, and the other end of the second switch is connected to the amplifier. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A voltage regulating system comprising:
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a load block comprises a first load block and a second load block, a first load current being required to drive the first load block, and a second load current being required to drive the second load block; and a voltage regulator provides the first and second load currents to the load block, wherein the voltage regulator comprises a first transistor and a second transistor connected in parallel between a power source terminal and the load block, wherein, when driving the first load block, the second transistor of the voltage regulator is disabled and the first transistor of the voltage regulator is enabled to generate the first load current, and wherein, when driving the second load block, the first transistor and the second transistor of the voltage regulator are enabled to generate the second load current. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A memory chip comprising:
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a memory cell array comprising a plurality of memory cells; and a voltage regulator configured to generate a load current to apply the load current to the memory cells, wherein the voltage regulator comprises; a power source terminal configured to supply a power source voltage; an output terminal configured to output the load current; a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first load current, and wherein the first transistor provides the first load current to drive N memory cells (N is a natural number) among the plurality of memory cells; and a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second load current larger than the first load current, and wherein the second transistor provides the second load current to drive M memory cells (M is a natural number greater than N) among the plurality of memory cells, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode. - View Dependent Claims (28, 29)
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30. A memory device comprising:
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a plurality of memory chips; and a controller configured to generate a load current and drive the memory chips using the load current, wherein the controller comprises a voltage regulator, and the voltage regulator comprises; a power source terminal configured to supply a power source voltage; an output terminal configured to output the load current; a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first load current, and wherein the first transistor provides the first load current to drive N memory chips (N is a natural number) among the plurality of memory chips; and a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second load current larger than the first load current, and wherein the second transistor provides the second load current to drive M memory chips (M is a natural number greater than N) among the plurality of memory chips, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.
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31. A voltage regulator comprising:
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a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; an amplifier amplifying at least a portion of a voltage of the output terminal; a first transistor connected between the power source terminal and the output terminal; and a second transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first current and the second transistor is disabled, and wherein, in a second mode, the first transistor is enabled by a signal applied from an amplifier to generate the first current and the second transistor is enabled by a signal applied from an amplifier to generate a second current. - View Dependent Claims (32, 33, 34, 35)
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Specification