VOLTAGE REGULATOR, VOLTAGE REGULATING SYSTEM, MEMORY CHIP, AND MEMORY DEVICE

• US 20140016425A1
• Filed: 05/15/2013
• Published: 01/16/2014
• Est. Priority Date: 07/12/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Joo-Sung, Heo, Dong-Hun
• Granted Patent: US 9,188,999 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H02J 1/00 Circuit arrangements for dc mains or dc distribution networks

Abstract

A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.

Claims

1. A voltage regulator comprising:

a power source terminal configured to supply a power source voltage;

an output terminal configured to output a load current;

a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first current, and wherein the first transistor outputs the first current to the output terminal; and

a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second current different from the first current, and wherein the second transistor outputs the second current to the output terminal,

wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.

2. The voltage regulator of claim 1, wherein a size of the first transistor is different from a size of the second transistor.

3. The voltage regulator of claim 2, wherein the size of the second transistor is larger than the size of the first transistor.

4. The voltage regulator of claim 1, wherein the second current is larger than the first current.

5. The voltage regulator of claim 1, wherein the first mode comprises a power saving mode and the second mode comprises an active mode.

6. The voltage regulator of claim 1, further comprising a feedback network connected between output terminal and the amplifier,

wherein the first transistor and the second transistor are connected in parallel between the power source terminal and the output terminal.

7. The voltage regulator of claim 1, wherein the load current is the first current in the first mode, and the load current is a sum of the first current and the second current in the second mode.

8. The voltage regulator of claim 1, further comprising a third transistor connected between the power source terminal and the output terminal, wherein, in a third mode different from the first and second modes, the third transistor is enabled by a signal applied from the amplifier to generate a third current different from the first and second currents, and wherein the third transistor outputs the third current to the output terminal.

9. The voltage regulator of claim 8, wherein the first transistor is enabled in the third mode,

the second transistor is enabled in the third mode, and

the third transistor is disabled in the first and second modes.

10. The voltage regulator of claim 9, wherein a size of the third transistor is larger than a size of the second transistor, and

the size of the second transistor is larger than a size of the first transistor.

11. A voltage regulator comprising:

a power source terminal configured to supply a power source voltage;

an output terminal configured to output a load current;

a first transistor which have a first terminal connected to the power source terminal, a second terminal connected to the output terminal, and a gate terminal connected to an amplifier; and

a second transistor which have a first terminal connected to the power source terminal, a second terminal connected to the output terminal, and a gate terminal connected to one end of each of a first switch and a second switch,

wherein the other end of the first switch is connected to the power source terminal, and the other end of the second switch is connected to the amplifier.

12. The voltage regulator of claim 11, wherein the first switch is turned on in a first mode, and turned off in a second mode and wherein the second mode is different from the first mode.

13. The voltage regulator of claim 12, wherein the second switch is turned off in the first mode, and turned on in the second mode.

14. The voltage regulator of claim 13, wherein the first mode comprises a power saving mode, and the second mode comprises an active mode.

15. The voltage regulator of claim 11, wherein the first transistor and the second transistor comprise PMOS transistors.

16. The voltage regulator of claim 11, further comprising a third transistor having a first terminal connected to the power source terminal, a second terminal connected to the output terminal, and a gate terminal connected to one end of each of a third switch and a fourth switch,

wherein the other end of the third switch is connected to the power source terminal, and the other end of the fourth switch is connected to the amplifier.

17. The voltage regulator of claim 16, wherein, in a first mode, the first switch and the third switch are turned on, and the second switch and the fourth switch are turned off,

wherein in a second mode different from the first mode, the second switch and the third switch are turned on, and the first switch and the fourth switch are turned off, and

wherein in a third mode different from the first and second modes, the second switch and the fourth switch are turned on, and the first switch and the third switch are turned off.

18. The voltage regulator of claim 11, wherein a size of the first transistor is different from a size of the second transistor.

19. The voltage regulator of claim 18, wherein the size of the second transistor is larger than the size of the first transistor.

20. A voltage regulating system comprising:

a load block comprises a first load block and a second load block, a first load current being required to drive the first load block, and a second load current being required to drive the second load block; and

a voltage regulator provides the first and second load currents to the load block,

wherein the voltage regulator comprises a first transistor and a second transistor connected in parallel between a power source terminal and the load block,

wherein, when driving the first load block, the second transistor of the voltage regulator is disabled and the first transistor of the voltage regulator is enabled to generate the first load current, and

wherein, when driving the second load block, the first transistor and the second transistor of the voltage regulator are enabled to generate the second load current.

21. The voltage regulating system of claim 20, wherein a magnitude of a first current generated by the first transistor is different from a magnitude of a second current generated by the second transistor.

22. The voltage regulating system of claim 21, wherein the magnitude of the second current is larger than the magnitude of the first current.

23. The voltage regulating system of claim 22, wherein the second load current is a sum of the first current and the second current.

24. The voltage regulating system of claim 20, wherein the load block further comprises a third load block, a third load current being required to drive the third load block,

wherein the voltage regulator further comprises a third transistor connected in parallel between the power source terminal and the load block,

wherein, when driving the first load block, the second transistor and the third transistor of the voltage regulator are disabled and the first transistor of the voltage regulator is enabled to generate the first load current,

wherein, when driving the second load block, the third transistor of the voltage regulator is disabled, and the first transistor and the second transistor of the voltage regulator are enabled to generate the second load current, and

wherein, when driving the third load block, the first transistor, the second transistor and the third transistor of the voltage regulator are enabled to generate the third load current.

25. The voltage regulating system of claim 24, wherein a magnitude of a third current generated by the third transistor is larger than a magnitude of a second current generated by the second transistor, and the magnitude of the second current generated by the second transistor is larger than a magnitude of a first current generated by the first transistor.

26. The voltage regulating system of claim 25, wherein the third load current is a sum of the first current, the second current and the third current.

27. A memory chip comprising:

a memory cell array comprising a plurality of memory cells; and

a voltage regulator configured to generate a load current to apply the load current to the memory cells,

wherein the voltage regulator comprises;

a power source terminal configured to supply a power source voltage;

an output terminal configured to output the load current;

a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first load current, and wherein the first transistor provides the first load current to drive N memory cells (N is a natural number) among the plurality of memory cells; and

a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second load current larger than the first load current, and wherein the second transistor provides the second load current to drive M memory cells (M is a natural number greater than N) among the plurality of memory cells,

wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.

28. The memory chip of claim 27, wherein the voltage regulator is disposed in a controller of the memory chip.

29. The memory chip of claim 27, wherein the first mode and the second mode are determined by an address signal.

30. A memory device comprising:

a plurality of memory chips; and

a controller configured to generate a load current and drive the memory chips using the load current,

wherein the controller comprises a voltage regulator, and

the voltage regulator comprises;

a power source terminal configured to supply a power source voltage;

an output terminal configured to output the load current;

a first transistor connected between the power source terminal and the output terminal, wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first load current, and wherein the first transistor provides the first load current to drive N memory chips (N is a natural number) among the plurality of memory chips; and

a second transistor connected between the power source terminal and the output terminal, wherein, in a second mode, the second transistor is enabled by a signal applied from the amplifier to generate a second load current larger than the first load current, and wherein the second transistor provides the second load current to drive M memory chips (M is a natural number greater than N) among the plurality of memory chips,

wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.

31. A voltage regulator comprising:

a power source terminal configured to supply a power source voltage;

an output terminal configured to output a load current;

an amplifier amplifying at least a portion of a voltage of the output terminal;

a first transistor connected between the power source terminal and the output terminal; and

a second transistor connected between the power source terminal and the output terminal,

wherein, in a first mode, the first transistor is enabled by a signal applied from an amplifier to generate a first current and the second transistor is disabled, and

wherein, in a second mode, the first transistor is enabled by a signal applied from an amplifier to generate the first current and the second transistor is enabled by a signal applied from an amplifier to generate a second current.

32. The voltage regulator of claim 31, wherein a size of the first transistor is different from a size of the second transistor.

33. The voltage regulator of claim 31, wherein the second current is larger than the first current.

34. The voltage regulator of claim 31, wherein the first mode comprises a power saving mode and the second mode comprises an active mode.

35. The voltage regulator of claim 31, wherein the load current is the first current in the first mode, and the load current is a sum of the first current and the second current in the second mode.