BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS

• US 20140097434A1
• Filed: 10/04/2012
• Published: 04/10/2014
• Est. Priority Date: 10/04/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ellis-Monaghan, John J., Hauser, Michael J., He, Zhong-Xiang, Liu, Xuefeng, Phelps, Richard A., Rassel, Robert M., Stamper, Anthony K.
• Granted Patent: US 8,809,155 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0808 Varactor diodes
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Claims

1. A method of fabricating a device structure, the method comprising:

forming a first conductive layer on a dielectric layer;

forming a semiconductor layer on the first conductive layer, the semiconductor layer comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state;

forming a source region and a drain region in the semiconductor layer;

forming an insulator layer on the semiconductor layer; and

forming a second conductive layer on the insulator layer.

2. The method of claim 1 wherein forming the semiconductor layer on the first conductive layer comprises:

depositing the silicon-containing semiconductor material in the amorphous state on the first conductive layer to form the semiconductor layer.

3. The method of claim 2 comprising:

applying a patterned mask partially covering the semiconductor layer; and

after the mask is applied, etching the semiconductor layer selective to the first conductive layer to form a semiconductor body of the device structure where the semiconductor layer is partially covered by the patterned mask.

4. The method of claim 3 comprising:

after the semiconductor layer is etched, laser annealing the semiconductor body to convert the silicon-containing semiconductor material from the amorphous state to the polycrystalline state.

5. The method of claim 1 further comprising:

applying a first mask partially covering the second conductive layer;

after the first mask is applied, etching the second conductive layer selective to the semiconductor layer to form a first electrode;

applying a second mask partially covering the semiconductor layer and the insulator layer and covering the first electrode; and

after the second mask is applied, etching the semiconductor layer and the insulator layer selective to the first conductive layer to respectively form a semiconductor body and an electrode insulator separating the first electrode from the semiconductor body.

6. The method of claim 5 further comprising:

applying a third mask partially covering the first conductive layer and covering the first electrode, the dielectric layer, and the semiconductor body; and

after the third mask is applied, etching the first conductive layer selective to the dielectric layer to form a wire defining a second electrode of the device structure.

7. The method of claim 6 further comprising:

forming a layer of a silicide-forming metal between the semiconductor layer and the first conductive layer,

wherein the layer of the silicide-forming metal is partially covered by the second mask and is etched when the first conductive layer is etched.

8. The method of claim 5 further comprising:

forming a layer of a silicide-forming metal between the semiconductor layer and the first conductive layer,

wherein the layer of the silicide-forming metal is partially covered by the second mask and is etched when the semiconductor layer and the insulator layer are etched.

9-20. -20. (canceled)