FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

• US 20140209908A1
• Filed: 04/01/2014
• Published: 07/31/2014
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cooney, Edward C. III, Dunn, James S., Martin, Dale W., Shi, Leathen, Sprogis, Edmund J., Tsang, Cornelia K., Musante, Charles S., Rainey Lawrence, BethAnn
• Granted Patent: US 9,355,936 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05687 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05688
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/80011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80013 : Plasma cleaning
• CPC Class Codes: H01L 2224/80075 : being inert
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/804 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/80487 : Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/80488
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80907 : Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
• CPC Class Codes: H01L 2224/80948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/4825 : for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 29/1054 : with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Claims

1. A bonded substrate assembly comprising:

a device substrate including a first surface, a second surface opposite to the first surface, a plurality of device structures on the first surface, and an interconnect structure for the device structures, the interconnect structure including an interlayer dielectric layer with a top surface, a first conductive feature projecting above the top surface, and a second conductive feature projecting above the top surface, the first and second conductive features each having a height measured relative to the top surface of the interlayer dielectric layer;

a final handle substrate bonded to the second surface of the device substrate; and

at least one insulator layer on the top surface of the interlayer dielectric layer, the at least one insulator layer having a planar top surface and a thickness greater than the height of the first and second conductive features.

2. The bonded substrate assembly of claim 1 wherein the second conductive feature separated by a gap from the first conductive feature, and the at least one insulator layer fills the gap.

3. The bonded substrate assembly of claim 2 wherein the at least one insulator layer comprises a first insulator layer comprised of a first dielectric material and a second insulator layer comprised of a second dielectric material, the first insulator layer fills the gap, and at least one of the first and second conductive features is disposed between a portion of the first dielectric material and the top surface of the interlayer dielectric layer.

4. The bonded substrate assembly of claim 3 wherein the first and second dielectric materials are comprised of silicon dioxide.

5. The bonded substrate assembly of claim 2 wherein the at least one insulator layer comprises a first insulator layer comprised of a first dielectric material and a second insulator layer comprised of a second dielectric material, the first insulator layer including a portion that fills the gap, and the first and second insulator layers include portions that define a composite layer that covers the first and second conductive features and the portion of the first insulator layer.

6. The bonded substrate assembly of claim 1 wherein the at least one insulator layer is comprised of a dielectric material that is free of voids.

7. The bonded substrate assembly of claim 1 further comprising:

a temporary handle wafer removably bonded to the planar top surface of the at least one insulator layer.

8. The bonded substrate assembly of claim 7 further comprising:

an adhesive layer between the temporary handle wafer and the planar top surface of the at least one insulator layer.

9. The bonded substrate assembly of claim 1 further comprising:

a layer comprising a dielectric material compositionally different from the dielectric material of the at least one insulator layer, the layer directly contacting the planar top surface of the at least one insulator layer and having a uniform thickness.

10. The bonded substrate assembly of claim 1 wherein at least one of the first and second conductive features is disposed between the planar top surface of the at least one insulator layer and the top surface of the interlayer dielectric layer.

11. The bonded substrate assembly of claim 1 wherein the device substrate includes a device layer and a buried insulator layer each extending laterally to a perimeter of the device substrate, and the second surface of the device substrate is a surface comprising the buried insulator layer.

12. The bonded substrate assembly of claim 1 wherein the final handle substrate is comprised of sapphire, and the second surface of the device substrate is an insulator layer.

13. The bonded substrate assembly of claim 1 wherein the device substrate includes a first product chip, a second product chip, and a kerf street between the first product chip and the second product chip, the device structures and the interconnect structure are on the first product chip, and the at least one insulator layer fills the kerf street to provide the planar top surface.

14. The bonded substrate assembly of claim 13 further comprising:

a test pad having a height measured relative to the top surface of the interlayer dielectric layer,

wherein the thickness of the at least one insulator layer greater than the height of the test pad.

15. The bonded substrate assembly of claim 1 wherein the first and second conductive features are each selected a wire used to transfer signals and power, a power distribution pad, an input/output pad, or a dummy pad.

16. A design structure readable by a machine used in design, manufacture, or simulation of an integrated circuit, the design structure comprising:

a device substrate including a first surface, a second surface opposite to the first surface, a plurality of device structures on the first surface, and an interconnect structure for the device structures, the interconnect structure including an interlayer dielectric layer with a top surface, a first conductive feature projecting above the top surface, and a second conductive feature projecting above the top surface, the first and second conductive features each having a height measured relative to the top surface;

a final handle substrate bonded to the second surface of the device substrate; and

at least one insulator layer on the top surface of the interlayer dielectric layer, the at least one insulator layer having a planar top surface and a thickness greater than the height of the first and second conductive features.

17. The design structure of claim 16 wherein the design structure comprises a netlist.

18. The design structure of claim 16 wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

19. The design structure of claim 16 wherein the design structure resides in a programmable gate array.