Barrier Layer for FinFET Channels

• US 20140264592A1
• Filed: 03/12/2013
• Published: 09/18/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Oxland, Richard Kenneth, van Dal, Mark, Holland, Martin Christopher, Vellianitis, Georgios
• Granted Patent: US 9,214,555 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

Claims

1. An integrated circuit device, comprising:

a semiconductor body;

a FinFET fin formed on the semiconductor body;

a channel region formed in a first layer of epitaxially grown semiconductor that is part of the fin; and

an insulating layer underneath the channel region, the insulting layer being formed from oxidizing a semiconductor that previously formed part of the fin.

2. The device of claim 1, wherein:

the semiconductor of the channel region is formed in a layer of semiconductor having a first composition;

the insulating layer is an oxidation product of a layer of a semiconductor having a second, different composition; and

a layer of a semiconductor of the second composition oxidizes through the thickness of the fin more rapidly than the layer having the first semiconductor composition.

3. The device of claim 1 wherein the second semiconductor composition is an aluminum compound.

4. The device of claim 1, further comprising:

an interface control layer between the first layer and the insulating layer, the interface control layer being formed from semiconductor composition having a bandgap substantially larger than that of the first layer.

5. The device of claim 4, wherein the interface control layer is formed from a composition selected from the group consisting of:

InP, GaAs, Si, SiGe.

6. The device of claim 4, further comprising:

a buffer layer of semiconductor underneath the insulating layer, the buffer layer forming part of the fin.

7. The device of claim 6, wherein:

the buffer layer has a thickness in the range from 20 to 300 nm;

the insulating layer has a thickness in the range from 2 to 50 nm; and

the interface control layer has a thickness in the range from 0.5 to 5 nm.

8. The device of claim 1, further comprising:

an interface control layer between the first layer and the insulating layer, the interface control layer forming a low defectivity interface with the oxidized layer.

9. The device of claim 1, further comprising:

a buffer layer of semiconductor underneath the insulating layer, the buffer layer forming part of the fin.

10. The device of claim 1, further wherein the first layer is a compound of Group III and Group V semiconductors.

11. The device of claim 5, further wherein the first layer is a compound of Group III and Group V semiconductors.

12. The device of claim 1, wherein the insulating layer extends the entire length of the fin.

13. The device of claim 1, wherein the FinFET is of the p-type.

14. An integrated circuit device, comprising:

a semiconductor body;

a FinFET fin formed on the semiconductor body, the FinFET including a channel that is epitaxially grown from a single crystal; and

a current-blocking layer underneath the channel, the current-blocking layer being formed from oxidized semiconductor.

15. The device of claim 14, further wherein the channel is a single crystal of semiconductor.

16. A method of manufacturing an integrated circuit device, comprising:

forming a FinFET fin including a channel region by epitaxial growth; and

forming an insulating layer underneath the channel region by oxidizing a layer of the fin.

17. The method of claim 16, wherein oxidizing electrically isolates the channel region from an underlying semiconductor body.

18. The method of claim 16, wherein:

forming the FinFET comprises epitaxially growing a first layer of a first semiconductor composition and a second layer of a second, different semiconductor composition over the first layer;

oxidizing comprises oxidizing the first layer; and

the composition of the first layer has a greater susceptibility to oxidation than the composition of the second layer.

19. The method of claim 18, wherein the first layer exhibits self-limiting oxidation.

20. The method of claim 16, wherein the source of oxygen for oxidizing the layer of the fin is an adjacent dielectric solid.

21. The method of claim 16, wherein:

forming the FinFET comprises epitaxially growing a first layer of a first semiconductor composition, a second layer of a second, different semiconductor composition over the first layer, and third layer of a third semiconductor composition different than the second layer over the second layer;

oxidizing comprises oxidizing the first layer; and

the semiconductor of the second layer has a bandgap larger than that of the third layer.