DIRECT EXTERNAL INTERCONNECT FOR EMBEDDED INTERCONNECT BRIDGE PACKAGE

• US 20140264791A1
• Filed: 03/14/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Mathew J. Manusharow
• Inventors: Mallik, Debendra, MANUSHAROW, MATHEW J.
• Granted Patent: US 8,901,748 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA

Abstract

An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions.

Claims

1. A semiconductor package comprising:

a substrate;

a first semiconductor die having a first bridge interconnect region;

a second semiconductor die having a second bridge interconnect region;

a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region; and

an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply an external connection to the first and second bridge interconnect regions.

2. The package of claim 1, further comprising a plurality of vias through the substrate to connect the external connection rail to a power supply outside the package.

3. The package of claim 1, wherein the first contact area comprises data contacts to connect to the bridge and wherein the external connection rail comprises a first area between the first and second die coupled to vias for power and a second area extending into the first bridge interconnect region to supply power to contacts within the first bridge interconnect region.

4. The package of claim 3, wherein the external connection rail is further connected to the bridge to provide power to isolate the bridge interconnect region.

5. The package of claim 1, wherein the external connection rail is not embedded in the substrate.

6. The package of claim 1, wherein the external connection rail is above the substrate.

7. The package of claim 1, wherein the substrate has a top surface within the package to which the first and second dies are attached and wherein the external connection rail is attached to the top surface of the substrate.

8. The package of claim 1, further comprising a dielectric layer over the bridge and wherein the external connection rail is over the dielectric layer

9. The package of claim 1, wherein the first die is a processor die and the second die is a memory die.

10. An electronic computing device comprising:

a display;

a user input device; and

a processor to receive inputs from the user input device and present results on the display, the processor being packaged in a package having;

a substrate;

a first semiconductor die having a first bridge interconnect region;

a second semiconductor die having a second bridge interconnect region;

a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region; and

an external connection rail above the bridge extending between the interconnect bridge and the first and second semiconductor dies to supply an external connection to the first and second bridge interconnect regions.

12. The device of claim 10, wherein the external connection rail is above the substrate.

13. The device of claim 10, wherein the processor package includes at least one memory die.

11. The device of claim 11, further comprising an internal power supply to power the display and the processor, wherein the rail is connected to the internal power supply and to the bridge to provide power to isolate the bridge interconnect region.

14-18. -18. (canceled)

19. A semiconductor package comprising:

a substrate;

a first semiconductor die having a first bridge interconnect region;

a second semiconductor die having a second bridge interconnect region;

means embedded in the substrate for bridging connections between the first and second die, the means for bridging having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region; and

means for externally connecting power, the external power means having an external connection rail extending between the means for bridging and the first and second semiconductor dies to supply external connections to the first and second bridge interconnect regions.

20. The package of claim 19, further comprising means extending through the substrate for connecting the external connection rail to a power supply outside the package.