APPARATUS AND METHOD FOR CONTROLLING MULTI-WAY NAND FLASHES BY USING INPUT-OUTPUT PINS
First Claim
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1. A multi-way NAND flash control apparatus for controlling a plurality of NAND flashes, the apparatus comprising:
- a NAND flash monitor to verify a status of each of the plurality of NAND flashes using a read status command to check whether an internal operation of each of the NAND flashes is normally performed; and
a scheduler to determine a priority order in which each of the plurality of NAND flashes is to occupy an input/output (I/O) bus, based on the verified status.
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Abstract
The present invention relates to an apparatus and method for controlling multi-way NAND flashes using input-output pins. The apparatus for controlling multi-way NAND flashes includes: a NAND flash monitor for confirming each state of a plurality of NAND flashes by using a read status command which checks whether an inner operation of the NAND flash is performed normally; and a scheduler for determining the order in which each of the NAND flashes occupies an input-output bus.
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Citations
15 Claims
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1. A multi-way NAND flash control apparatus for controlling a plurality of NAND flashes, the apparatus comprising:
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a NAND flash monitor to verify a status of each of the plurality of NAND flashes using a read status command to check whether an internal operation of each of the NAND flashes is normally performed; and a scheduler to determine a priority order in which each of the plurality of NAND flashes is to occupy an input/output (I/O) bus, based on the verified status. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A multi-way NAND flash control method of controlling a plurality of NAND flashes, the method comprising:
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verifying, by a NAND flash control apparatus, a status of each of the NAND flashes using a read status command to check whether an internal operation of each of the NAND flashes is normally operated; and determining a priority order in which each of the NAND flashes is to occupy an input/output (I/O) bus, based on the verified status. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A NAND flash memory device comprising:
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a plurality of NAND flashes; a register to store a command for an operation to be performed by each of the NAND flashes and information on an address of a NAND flash performing the operation; a NAND flash controller to verify a status of each of the NAND flashes using a read status command stored in the register to check whether an internal operation of each of the NAND flashes is normally performed, and determine a priority order in which each of the NAND flashes is to occupy an input/output (I/O) bus, based on the verified status; and a buffer to temporarily store data transmitted between each of the NAND flashes and the NAND flash controller. - View Dependent Claims (14, 15)
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Specification