APPARATUS AND METHOD FOR CONTROLLING MULTI-WAY NAND FLASHES BY USING INPUT-OUTPUT PINS

• US 20150006794A1
• Filed: 12/10/2012
• Published: 01/01/2015
• Est. Priority Date: 12/23/2011
• Status: Abandoned Application

• Current Assignee: Industry-University Cooperation Foundation Hanyang University
• Original Assignee: Industry-University Cooperation Foundation Hanyang University
• Inventors: Kang, Soo Yong, Won, You Jip, Cha, Jae Hyuk, Yoon, Sung Roh, Choi, Jong Moo, Rhee, Myung Hyun
• Application Number:
  US14/366,496
• Publication Number:
  US 20150006794A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present invention relates to an apparatus and method for controlling multi-way NAND flashes using input-output pins. The apparatus for controlling multi-way NAND flashes includes: a NAND flash monitor for confirming each state of a plurality of NAND flashes by using a read status command which checks whether an inner operation of the NAND flash is performed normally; and a scheduler for determining the order in which each of the NAND flashes occupies an input-output bus.

Claims

1. A multi-way NAND flash control apparatus for controlling a plurality of NAND flashes, the apparatus comprising:

a NAND flash monitor to verify a status of each of the plurality of NAND flashes using a read status command to check whether an internal operation of each of the NAND flashes is normally performed; and

a scheduler to determine a priority order in which each of the plurality of NAND flashes is to occupy an input/output (I/O) bus, based on the verified status.

2. The apparatus of claim 1, wherein the NAND flash monitor determines a time for verifying the status of each of the NAND flashes by using a polling scheme, based on a pre-generated timetable.

3. The apparatus of claim 2, wherein the timetable is generated based on information on a minimum internal operation time of a command for each of the NAND flashes, and information on an internal operation time of each of the NAND flashes with respect to the command.

4. The apparatus of claim 1, wherein the NAND flash monitor verifies whether the internal operation is completed using the read status command.

5. The apparatus of claim 1, wherein the NAND flash monitor verifies the status of each of the plurality of NAND flashes using the read status command, in lieu of a ready/busy (R/B) pin.

6. The apparatus of claim 1, wherein the scheduler determines a priority order in which each of the NAND flashes is to occupy the I/O bus using an interleaving scheme.

7. A multi-way NAND flash control method of controlling a plurality of NAND flashes, the method comprising:

verifying, by a NAND flash control apparatus, a status of each of the NAND flashes using a read status command to check whether an internal operation of each of the NAND flashes is normally operated; and

determining a priority order in which each of the NAND flashes is to occupy an input/output (I/O) bus, based on the verified status.

8. The method of claim 7, further comprising:

determining a time for verifying the status of each of the NAND flashes by using a polling scheme, based on a pre-generated timetable.

9. The method of claim 8, wherein the timetable is generated based on information on a minimum internal operation time of a command for each of the NAND to flashes, and information on an internal operation time of each of the NAND flashes with respect to the command.

10. The method of claim 7, wherein the verifying comprises verifying whether the internal operation is completed using the read status command.

11. The method of claim 7, wherein the verifying comprises verifying the status of each of the plurality of NAND flashes using the read status command, in lieu of a ready/busy (R/B) pin.

12. The method of claim 7, wherein the determining comprises determining the priority order in which each of the NAND flashes is to occupy the I/O bus using an interleaving scheme.

13. A NAND flash memory device comprising:

a plurality of NAND flashes;

a register to store a command for an operation to be performed by each of the NAND flashes and information on an address of a NAND flash performing the operation;

a NAND flash controller to verify a status of each of the NAND flashes using a read status command stored in the register to check whether an internal operation of each of the NAND flashes is normally performed, and determine a priority order in which each of the NAND flashes is to occupy an input/output (I/O) bus, based on the verified status; and

a buffer to temporarily store data transmitted between each of the NAND flashes and the NAND flash controller.

14. The device of claim 13, wherein the NAND flash controller determines a time for verifying the status of each of the NAND flashes using a polling scheme based on a timetable generated based on information on a minimum internal operation time of a command for each of the NAND flashes, and information on an internal operation time of each of the NAND flashes with respect to the command.

15. The device of claim 13, wherein the NAND flash controller verifies whether the internal operation is completed using the read status command, in lieu of a ready/busy (R/B) pin, and

determines the priority order in which each of the NAND flashes is to occupy the I/O bus using an interleaving scheme.