PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION
7 Assignments
0 Petitions
Accused Products
Abstract
A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.
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Citations
19 Claims
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1-6. -6. (canceled)
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7. A processing unit for a data processing system including a shared memory system, the processing unit comprising:
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a processor core; a cache memory coupled to the processor core, wherein the cache memory includes; a cache array; a directory of contents of the cache array, wherein entries in the cache array and directory have a set associative organization and are grouped in multiple congruence classes; and transactional memory tracking logic that tracks a transaction footprint including one or more cache lines in the cache array accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core; wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class, wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit for a data processing system including a shared memory system, the processing unit including; a processor core; a cache memory coupled to the processor core, wherein the cache memory includes; a cache array; a directory of contents of the cache array, wherein entries in the cache array and directory have a set associative organization and are grouped in multiple congruence classes; and transactional memory tracking logic that tracks a transaction footprint including one or more cache lines in the cache array accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core; wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class, wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set. - View Dependent Claims (15, 16, 17, 18, 19)
Specification