Decimation Synchronization in a Microphone

• US 20150055803A1
• Filed: 11/05/2014
• Published: 02/26/2015
• Est. Priority Date: 05/23/2013
• Status: Active Grant

• Current Assignee: Knowles Electronics Llc (Knowles Corporation)
• Original Assignee: Knowles Electronics Llc (Knowles Corporation)
• Inventors: Nandy, Dibyendu, Qutub, Sarmad, Popper, Robert A., Kassir, Thibault
• Granted Patent: US 9,711,166 B2
• Time in Patent Office: Days
• US Class Current: 381/111
• CPC Class Codes: G10L 25/48 specially adapted for particular use
• CPC Class Codes: H04R 2410/00 Microphones
• CPC Class Codes: H04R 2499/11 Transducers incorporated or for use in hand-held devices, e.g. mobile phones, PDA's, camera's
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

An external clock signal having a first frequency is received. A division ratio is automatically determined based at least in part upon a second frequency of an internal clock. The second frequency is greater than the first frequency. A decimation factor is automatically determined based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency. The division ratio is applied to the internal clock signal to reduce the first frequency to a reduced third frequency. The decimation factor is applied to the reduced third frequency to provide the predetermined desired sampling frequency. Data is clocked to a buffer using the predetermined desired sampling frequency.

Claims

1. A method, the method comprising:

receiving an external clock signal having a first frequency;

automatically determining a division ratio based at least in part upon a second frequency of an internal clock, the second frequency being greater than the first frequency;

automatically determining a decimation factor based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency;

applying the division ratio to the internal clock signal to reduce the first frequency to a reduced third frequency;

applying the decimation factor to the reduced third frequency to provide the predetermined desired sampling frequency;

clocking data to a buffer using the predetermined desired sampling frequency.

2. The method of claim 1, further comprising subsequently removing the external clock signal.

3. The method of claim 1 wherein the predetermined desired sampling frequency comprises a frequency rate of approximately 16 kHz.

4. An apparatus, the apparatus comprising:

interface circuitry having an input and output, the input configured to receive an external clock signal having a first frequency;

processing circuitry, the processing circuitry coupled to the interface circuitry and configured to automatically determine a division ratio based at least in part upon a second frequency of an internal clock, the second frequency being greater than the first frequency, the processing circuitry further configured to automatically determine a decimation factor based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency, the processing circuitry further configured to apply the division ratio to the internal clock signal to reduce the first frequency to a reduced third frequency and to apply the decimation factor to the reduced third frequency to provide the predetermined desired sampling frequency, the processing circuitry further configured to clock data to a buffer via the output using the predetermined desired sampling frequency.

5. The apparatus of claim 4, wherein the external clock signal is subsequently removed.

6. The apparatus of claim 4 wherein the predetermined desired sampling frequency comprises a frequency rate of approximately 16 kHz.