METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE

• US 20150106560A1
• Filed: 12/17/2014
• Published: 04/16/2015
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: PEREGO, Richard E., BATRA, Pradeep, WOO, Steven, LAI, Lawrence, YEUNG, Chi-Ming
• Granted Patent: US 9,043,513 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Claims

1. A dual-inline memory module (DIMM) comprising:

a module interface configured to receive module data into the DIMM using parallel data channels;

a non-volatile flash memory bank; and

one or more integrated circuits configured to receive the module data using the parallel data channels and to enable the module data to be written to a dynamic random access memory (DRAM) bank, read from the DRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the DRAM bank and a second addressing scheme employed by the non-volatile flash memory bank.

2. The DIMM of claim 1, wherein the DRAM bank is located outside of the integrated circuit.

3. The DIMM of claim 1, wherein the DRAM bank includes dynamic data rate (DDR) memory and the non-volatile flash memory bank includes a solid state disk (SSD).

4. The DIMM of claim 1, wherein the integrated circuit is configured to enable:

the module data to be written to the DRAM bank employing the first addressing scheme;

the module data written to the DRAM bank employing the first addressing scheme to be read;

the module data read from the DRAM bank to be translated from the first addressing scheme employed by the DRAM bank to the second addressing scheme employed by the non-volatile flash memory bank; and

the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme.

5. The DIMM of claim 1, wherein the integrated circuit further comprises a buffer.

6. The DIMM of claim 5, wherein the buffer further comprises:

a write buffer including a write data queue circuit; and

a read buffer including a read data queue circuit.

7. The DIMM of claim 5, wherein the integrated circuit is configured to enable:

the module data to be written from the buffer to the DRAM bank.

the module data to be read from the DRAM bank into the buffer; and

the module data to be written from the buffer to the non-volatile flash memory bank.

8. The DIMM of claim 1, wherein the integrated circuit further comprises:

a peripheral processor configured to execute commands; and

a controller configured to translate between the first addressing scheme employed by the DRAM bank and the second addressing scheme employed by the non-volatile flash memory bank according to instructions from the peripheral processor.

9. The DIMM of claim 1, further comprising a bridge circuit configured to enable the module data to be read from or written to the non-volatile flash memory bank.

10. The DIMM of claim 9, wherein the bridge circuit is configured to perform serialization or deserialization operations.

11. The DIMM of claim 10, wherein the bridge circuit is located within the integrated circuit.

12. A dual-inline memory module (DIMM) comprising:

a module interface configured to receive module data into the DIMM using parallel data channels;

a non-volatile flash memory bank; and

means for one or more integrated circuits configured to receive the module data using the parallel data channels and to enable the module data to be written to a dynamic random access memory (DRAM) bank, read from the DRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the DRAM bank and a second addressing scheme employed by the non-volatile flash memory bank.

13. The DIMM of claim 12, wherein the means for an integrated circuit is configured to enable:

the module data to be written to the DRAM bank employing the first addressing scheme;

the module data written to the DRAM bank employing the first addressing scheme to be read;

the module data read from the DRAM bank to be translated from the first addressing scheme employed by the DRAM bank to the second addressing scheme employed by the non-volatile flash memory bank; and

the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme.

14. The DIMM of claim 12, wherein the means for an integrated circuit further comprises a buffer.

15. The DIMM of claim 12, further comprising a bridge circuit configured to enable the module data to be read from or written to the non-volatile flash memory bank.

16. A system comprising:

a central processing unit (CPU) with a memory controller configured to direct delivery of module data from the CPU to module memory using parallel data channels; and

a dual-inline memory module (DIMM) configured to receive the module data from the CPU, including;

a module interface configured to receive the module data into the DIMM using parallel data channels,

a non-volatile flash memory bank, and

one or more integrated circuits configured to receive the module data using the parallel data channels and to enable the module data to be written to a dynamic random access memory (DRAM) bank, read from the DRAM bank, and written to the non-volatile flash memory bank, wherein the one or more integrated circuits are configured to translate between a first addressing scheme employed by the DRAM bank and a second addressing scheme employed by the non-volatile flash memory bank.

17. The system of claim 16, wherein the integrated circuit is configured to enable:

the module data to be written to the DRAM bank employing the first addressing scheme;

the module data written to the DRAM bank employing the first addressing scheme to be read;

the module data read from the DRAM bank to be translated from the first addressing scheme employed by the DRAM bank to the second addressing scheme employed by the non-volatile flash memory bank; and

the module data translated to the second addressing scheme employed by the non-volatile flash memory bank to be written to the non-volatile flash memory bank employing the second addressing scheme.

18. The system of claim 17, wherein the integrated circuit further comprises a buffer.

19. The system of claim 17, further comprising a bridge circuit configured to enable the module data to be read from or written to the non-volatile flash memory bank.

20. The system of claim 19, wherein the bridge circuit is configured to perform serialization or deserialization operations.