METHOD OF MANUFACTURING A DEVICE COMPRISING AN INTEGRATED CIRCUIT AND PHOTOVOLTAIC CELLS

• US 20150115387A1
• Filed: 10/28/2014
• Published: 04/30/2015
• Est. Priority Date: 10/29/2013
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: BUCKLEY, Julien, BEN JAMAA, Haykel
• Granted Patent: US 9,647,161 B2
• Time in Patent Office: Days
• US Class Current: 257/443
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 31/0475 PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays PV modules composed of a plurality of thin film solar cells deposited on the same substrate H01L31/046
• CPC Class Codes: H01L 31/0504 specially adapted for series or parallel connection of solar cells in a module
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

According to one embodiment, the present invention relates to a method for manufacturing a photovoltaic device comprising a photovoltaic cell or a plurality of photovoltaic cells (PV cells) connected to an electronic integrated circuit having at least one electrical contact area. A stack comprising the PV cell(s) is produced separately from the electronic integrated circuit, the electronic integrated circuit is then transferred to said stack comprising the PV cell(s). During this transfer, connection areas carried by the PV cell(s) are brought into contact with matching connection areas carried by the electronic integrated circuit.

Claims

1. A method for manufacturing a photovoltaic device comprising a photovoltaic cell or a plurality of photovoltaic cells (PV cells) connected to an electronic integrated circuit, the method comprising the following steps:

a step of executing a stack comprising the cell or the plurality of PV cells, the step of executing the stack comprising a step of executing the cell or the plurality of PV cells, which comprises, for each PV cell, the execution in a semi-conducting material of at least two regions having opposite P and N doping;

after the step of executing the cell or the plurality of PV cells, a cycle of steps of connection comprising at least executing the first connections comprising at least one receiving area intended to electrically connect the at least one PV cell with at least one electronic integrated circuit;

after the cycle of the steps of connection, a step of transferring, onto said stack comprising the cell or the plurality of PV cells, a previously manufactured electronic integrated circuit, with the step of transfer being executed so as to electrically connect the at least one receiving area with an electrical contact area carried by the electronic integrated circuit;

wherein the step of executing the cell or of the plurality of PV cells comprises at least the following step, executed from a stack comprising;

a substrate topped with an insulating layer and a semi-conducting layer, the semi-conducting layer comprising at least one upper portion extending from an upper face of the semi-conducting layer and having a P or N doping and a lower portion located under the upper portion and having a P or N doping opposite to the doping of the upper portion;

a step of forming the PV cell or PV cells by etching the semi-conducting layer so as to form respectively one or more island(s) distant from each other, each one comprising a superimposition of the lower and upper portions of the semi-conducting layer and having a front face formed by the upper portion, each island forming a PV cell.

2. A method according to claim 1, wherein the photovoltaic device comprises a plurality of photovoltaic cells (PV cells) and said cycle of steps of connection comprises the execution of a plurality of second electric connections to interconnect the PV cells of said plurality of PV cells.

3. A method according to claim 2, wherein the steps of forming the first connections and the second connections are executed simultaneously.

4. A method according to claim 2 wherein the steps of forming the first connections and the second connections are executed successively.

5. A method according to claim 1, wherein after the etching of the semi-conducting layer so as to form the island(s) and prior to the step of executing the cycle of the steps of electric connections, the method comprises a step of forming spacers on the sides of each island only

6. A method according to claim 1, wherein the execution of the first connections comprising at least one receiving area for an integrated circuit comprises the execution of at least said receiving area located on the insulating layer.

7. A method according to claim 1, wherein the step of forming each island by etching the semi-conducting layer is executed so as to preserve, at the root of each island a contact area formed in said lower portion of the semi-conducting layer and which is not located under said upper portion.

8. A method according to claim 7, wherein the contact area is doped so as to make it electrically conducting.

9. A method according to claim 8, wherein the photovoltaic device comprises a plurality of PV cells, wherein said cycle of steps of connection comprises the execution of a plurality of second electric connections to interconnect the PV cells of said plurality of PV cells and wherein the step of execution of a plurality of second electric connections to interconnect the PV cells comprises the execution of an electric connection connecting the contact area of a PV cell to said front face of another PV cell.

10. A method according to claim 1, wherein the step of forming each island by etching the semi-conducting layer is executed so as to stop the etching on the insulating layer out of the island(s).

11. A method according to claim 1, wherein the photovoltaic device comprises a plurality of PV cells, wherein said cycle of steps of connection comprises the execution of a plurality of second electric connections to interconnect the PV cells of said plurality of PV cells and wherein the execution of a plurality of second electric connections to interconnect the PV cells comprises the following steps:

etching, from a face of the stack comprising the PV cells formed by the islands, the whole thickness of the insulating layer and a part of the thickness of the substrate to form an opening out of each PV cell;

filling said openings with a conducting material and forming an electric connection between said conducting material filling the opening and said upper portion of the semi-conducting layer of the PV cell;

thinning the rear face of the substrate opposite the face of the substrate facing the PV cells, in order to lead until the openings, on said rear face, the openings filled with metal which then form through vias are reached;

etching, under the PV cells, the whole thickness of the insulating layer and the substrate to form, for each PV cell, an additional opening, with each additional opening extending from the rear face of the substrate and reaching the lower portion of the semi-conducting layer of each PV cell;

filling the additional openings with a conducting material so as to form vias connecting the rear face of the substrate to each PV cell;

depositing, on the rear face of the substrate, a conducting material to electrically connect at least some of said through vias connected to the lower portion of a PV cell to a via connected to the upper portion of another PV cell.

12. A method according to claim 1, wherein the photovoltaic device comprises a plurality of PV cells, wherein said cycle of steps of connection comprises the execution of a plurality of second electric connections to interconnect the PV cells of said plurality of PV cells and wherein the execution of a plurality of second electric connections to interconnect the PV cells comprises the following steps:

etching, under PV cells and from the rear face of the substrate, the whole thickness of the insulating layer and the substrate to form two openings for each PV cell, with each opening extending from the rear face and reaching the lower portion of the semi-conducting layer of each PV cell;

doping, for each PV cell, an area of the lower portion whereto one of the two openings leads, with such doping being opposite that of the lower portion;

filling, for each PV cell, the two openings with a conducting material so as to form vias connecting the rear face of the substrate of each PV cell;

forming, on the rear face of the substrate, electric connections so as to electrically connect two by two vias associated with two PV cells and leading to areas of the lower portion having opposite dopings.

13. A method according to claim 12, wherein after etching the two openings for each PV cell and prior to filling, for each PV cell, the two openings with a conducting material, a step of doping is executed, for each PV cell, of an area of the lower portion whereto the other one of said two openings leads, such doping being opposite that of the lower portion and has a level of doping at least 10 times and preferably at least 100 times greater than that of the lower portion.

14. A method according to claim 11, wherein the execution of the first connections comprising a receiving area for an integrated circuit comprises the execution of at least said receiving area located on the rear face of the substrate.

15. A method according to claim 11, wherein the execution of the first connections comprising a receiving area for an integrated circuit comprises the execution:

of at least one receiving area located on the insulating layer to receive a first integrated circuit on the face of the insulating layer turned in front of the PV cell(s);

of at least one receiving area located on the rear face of the substrate to receive a first integrated circuit on said rear face.

16. A method according to claim 1, wherein the stack comprising a substrate topped with an insulating layer and a semi-conducting layer is a substrate of the silicon on insulator (SOI) type wherein the insulating layer is made of a silicon oxide and wherein a step of doping the upper face of the semi-conducting layer is executed from the SOI substrate, so that the semi-conducting layer comprises said upper portion having a doping opposite that of said lower portion formed by the rest of the semi-conducting layer.

17. A method according to claim 1, wherein the stack comprising a substrate topped with an insulating layer is obtained by executing the following steps from a massive substrate made of a semi-conducting material:

N or P type doping of an upper part of the massive substrate to form the insulating layer of said stack;

transfer onto the upper part of a semi-conducting layer having a doping opposite that of the upper part of the massive substrate;

thinning of said transferred semi-conducting layer;

doping of the upper face of said transferred semi-conducting layer so that such transferred semi-conducting layer has an upper portion extending from the upper face thereof and having an opposite doping of a lower portion formed by the rest of said transferred semi-conducting layer.

18. A method according to claim 16, wherein said lower portion is formed of a first thickness portion having a P or N doping and another also P respectively N doped thickness portion but the doping level of which is at least 100 times greater than that of the first portion and is at least equal to 1 atom of the doping species for less than 1,000 atoms of the material forming the semi-conducting layer (P+ respectively N+ doping), said other portion being located between the insulating layer and said first P respectively N doped thickness portion and wherein said other thickness portion is in contact with the insulating layer and with said first thickness portion.

19. A method according to claim 1, wherein the photovoltaic device comprises a plurality of PV cells, wherein said cycle of connection steps comprises the execution of a plurality of second electric connections to interconnect the PV cells of said plurality of PV cells and wherein prior to the step of forming islands by etching of the semi-conducting layer to form the PV cells an insulating layer is positioned under the semi-conducting layer and a conducting pad, connected to the lower portion of the semi-conducting layer of the PV cell and extending laterally so as to have at least one first portion located under the PV cell and at least one second portion not located under the same PV cell, is formed inside the insulating layer and for each PV cell;

and wherein, the execution of a plurality of second electric connections to interconnect the PV cells comprises the following steps;

opening of the insulating layer under the second portion of the metallic pad of the PV cell, deposition of a conducting material in the opening and on a part of the side of another PV cell until the upper portion of such other PV cell is reached, so as to provide an electric connection between the lower portion and the upper portion of two PV cells.

20. A method according to claim 1, wherein the electronic integrated circuit comprises transistors more particularly complementary transistors (C) of the Metal Oxide semiconductor (MOS) type and/or memories and/or batteries and/or passive devices such as capacitances or inductors.

21. A method according to claim 1, wherein the transfer of the electronic integrated circuit causes, alone, the connection between the latter and at least some of the PV cells.

22. A photovoltaic device comprising one or several photovoltaic cell(s) (PV cells) and at least one electronic integrated circuit connected to the PV cell or to the plurality of PV cells, with the device comprising:

a substrate topped with an insulating layer and a semi-conducting layer positioned on a front face of the insulating layer, with the PV cell or the plurality of PV cells being formed in said semi-conducting layer;

wherein said front face of the insulating layer carries electric connections to interconnect the PV cells of said plurality of PV cells and other electric connections forming at least one receiving area so configured as to connect at least one PV cell with at least one electronic integrated circuit;

and in that said at least one electronic integrated circuit is positioned in contact with the receiving area in front of the front face of the insulating layer.

23. A photovoltaic device according to claim 22, wherein the photovoltaic device comprises a plurality of photovoltaic cells (PV cells) and wherein said front face of the insulating layer carries electric connections to interconnect the PV cells of said plurality of PV cells.

24. A photovoltaic device according to claim 22 comprising an additional electronic integrated circuit positioned in front of a rear face of the substrate, connected to the PV cell or to said plurality of PV cells so that said insulating layer is positioned between two electronic integrated circuits.

25. A photovoltaic device according to claim 22, wherein said receiving areas make it possible to connect, alone, the electronic integrated circuit with at least some of the PV cells.