STRUCTURE AND METHOD FOR TESTING STACKED CMOS STRUCTURE
First Claim
1. A test structure for testing a 3D semiconductor structure having a plurality of tiers, comprisingat least one conductive loop, each respective conductive loop having ends defining at least one opening therebetween and being embedded inside one or more of the plurality of tiers in the semiconductor structure;
- andat least two test pads on each respective conductive loop, the at least two test pads connected with respective ends of each respective conductive loop.
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Accused Products
Abstract
A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.
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Citations
20 Claims
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1. A test structure for testing a 3D semiconductor structure having a plurality of tiers, comprising
at least one conductive loop, each respective conductive loop having ends defining at least one opening therebetween and being embedded inside one or more of the plurality of tiers in the semiconductor structure; - and
at least two test pads on each respective conductive loop, the at least two test pads connected with respective ends of each respective conductive loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor structure having a plurality of tiers and comprising a test structure for testing the semiconductor structure, the test structure comprising
at least one conductive loop, each respective conductive loop having ends defining at least one opening therebetween and being embedded inside one or more of the plurality of tiers in the semiconductor structure; - and
at least two test pads on each respective conductive loop, the at least two test pads connected with respective ends of the at least one opening of each respective conductive loop. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor structure, comprising
a stacked complementary metal-oxide-semiconductor (CMOS) device having a plurality of tiers in a wafer, and a test structure for testing the semiconductor structure, the test structure comprising at least one conductive loop, each respective conductive loop having ends defining at least one opening therebetween and being embedded inside one or more of the plurality of tiers in the semiconductor structure; -
at least two test pads on each respective conductive loop, the at least two test pads connected with respective ends of the at least one opening of each respective conductive loop; a conductive mesh in a middle portion of the semiconductor structure, the conductive mesh routed through scribe lines within one respective tier of the semiconductor structure, and routed through inter-level vias connecting tiers in the semiconductor structure; and a plurality of additional test pads connected with the conductive mesh on a surface tier of the semiconductor structure; wherein the conductive mesh is configured to conduct a current between two of the plurality of test pads on the surface tier. - View Dependent Claims (20)
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Specification