MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

• US 20150162067A1
• Filed: 06/06/2014
• Published: 06/11/2015
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Bo-Yeun, YOON, Seok-Cheol, JANG, Ji-Eun
• Granted Patent: US 9,190,137 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh

Abstract

A memory may include a plurality of word lines coupled to one or more memory cells; a target address generation unit suitable for generating one or more target addresses using a stored address; and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

Claims

1. A memory comprising:

a plurality of word lines coupled to one or more memory cells;

a target address generation unit suitable for generating one or more target addresses using a stored address; and

a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command, which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

2. The memory of claim 1, further comprising an address detection unit suitable for detecting a highly active word line, which has been activated a number greater than or equal to a preset number or which has an activation frequency greater than or equal to a preset frequency, during a preset period.

3. The memory of claim 2, wherein the target address generation unit stores an address of the highly active word line, and

wherein the target address corresponds to a target word line adjacent to the highly active word line.

4. The memory of claim 1, wherein the control unit refreshes a target word line corresponding to the target address while the refresh command is inputted N times, and changes sequential order in which the target word line is refreshed during N times of input of the refresh commands.

5. The memory of claim 1, further comprising an address counting unit suitable for generating a counting address, a value of which is changed whenever a word line is refreshed.

6. The memory of claim 5, wherein the control unit comprises:

a refresh control unit suitable for enabling a first refresh signal in response to the refresh command, and enabling a second refresh signal in response to the refresh command at a random time; and

a row control unit suitable for refreshing a word line corresponding to the counting address in response to the first refresh signal, and refreshing a target word line corresponding to the target address in response to the second refresh signal.

7. The memory of claim 6, wherein the refresh control unit comprises:

a first refresh signal generator suitable for enabling the first refresh signal in response to the refresh command; and

a second refresh signal generator suitable for enabling the second refresh signal in response to the refresh command at a random time.

8. The memory of claim 7, wherein the second refresh signal generator comprises:

a first counter suitable for counting the refresh command and generating first counting information;

a second counter suitable for counting the refresh command and generating second counting information; and

a signal generator suitable for enabling the second refresh signal in response to the refresh command when the first counting information has a preset value, and controlling the first counter to initialize the first counting information to an initial value when the second counting information has a preset value.

9. The memory of claim 7, wherein the second refresh signal generator comprises:

a counter suitable for counting the refresh command and generating counting information;

a periodic signal generator suitable for generating a periodic signal which toggles at a preset period; and

a signal generator suitable for enabling the second refresh signal in response to the refresh command when the counting information has a preset value, and controlling the counter to initialize the counting information to an initial value in response to the periodic signal.

10. The memory of claim 7, wherein the second refresh signal generator comprises:

a random number generator suitable for generating a random number in response to the refresh command; and

a signal generator suitable for enabling the second refresh signal when the random number has a preset value.

11. The memory of claim 6, wherein the target address generation unit outputs the target address when the second refresh signal is enabled.

12. A memory system comprising:

a memory; and

a memory controller suitable for periodically inputting a refresh command to the memory,

wherein the memory comprises;

a plurality of word lines coupled to one or more memory cells;

a target address generation unit suitable for generating one or more target addresses using a stored address; and

a control unit suitable for sequentially refreshing the plurality of word lines in response to the refresh command, which is periodically inputted, and refreshing a word line corresponding to the target address in response to the refresh command at a random time.

13. The memory system of claim 12, wherein the memory detects a highly active word line, which has been activated a number of times greater than or equal to a preset number or which has an activation frequency greater than or equal to a preset frequency, during a preset period.

14. The memory system of claim 13, wherein the target address generation unit stores an address of the highly active word line, and

wherein the target address corresponds to a target word line adjacent to the highly active word line.

15. The memory system of claim 12, wherein the memory controller inputs an active command and an address to the memory between periodical inputs of the refresh commands.

16. The memory system of claim 12, wherein the memory refreshes a target word line corresponding to the target address while the refresh command is inputted N times, and changes sequential order in which the target word line is refreshed during N times of input of the refresh commands.

17. The memory system of claim 16, wherein the memory generates counting information, a value of which is changed whenever a word line is refreshed, refreshes the target word line in response to the refresh command when the counting information has a preset value, and initializes the counting information to an initial value at a preset time.

18. A memory comprising:

a plurality of word lines; and

a refreshing unit suitable for refreshing one or more of the plurality of word lines in response to one or more of each input of a periodical refresh command and one or more word lines adjacent to a highly active word line in response to every N-th input count of the periodical refresh command,

wherein the refreshing unit initializes the input count after every M-th input of the periodical refresh command.

19. The memory of claim 18, wherein a number of activations of the highly active word line is greater than or equal to a preset number.

20. The memory of claim 18, wherein

a frequency of activation of the highly active word line is greater than or equal to a preset frequency, during a preset period.