COMPUTER ARCHITECTURE TO PROVIDE FLEXIBILITY AND/OR SCALABILITY

• US 20150186319A1
• Filed: 12/26/2013
• Published: 07/02/2015
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Morgan, John M., Goldschmidt, Marc A., Pullin, Edward J., Blevins, Dirk F.
• Granted Patent: US 9,792,243 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Claims

1. A rack-scale architecture comprising:

a surface defining a slot to accommodate a hardware module; and

a peripheral component interconnect express (PCIe) link to directly couple the slot with a network fabric.

2. The architecture of claim 1, further including a surface defining two or more slots, wherein a PCIe link directly couples each of the two or more slots with the network fabric.

3. The architecture of claim 2, further including one or more of:

a one rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel input/output (I/O);

a two rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel I/O;

or

a four rack unit implementation, wherein at least two slots accommodate a processor module, and wherein an additional PCIe link directly couples each of the at least two slots with a back panel I/O.

4. The architecture of claim 2, further including one or more of:

at least two slots that accommodate a respective processor module, wherein the network fabric is utilized when the respective processor modules communicate across the PCIe link directly coupling each of the at least two slots with the network fabric;

or

at least two slots that accommodate a respective processor module, wherein the network fabric is bypassed when the respective processor modules communicate across an additional PCIe link directly coupling each of the at least two slots with a bridge.

5. The architecture of claim 2, further including one or more of:

an additional PCIe link directly coupling a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is bypassed when the processor module and the I/O module communicate across the additional PCIe link;

or

a dual star PCIe link directly coupling four slots with each other, wherein the network fabric is bypassed when at least two hardware modules communicate across the dual star PCIe link.

6. The architecture of claim 1, further including one or more of:

a user specific I/O to provide user defined functionality;

or

a management element to provide management functionality.

7. The architecture of claim 1, wherein the hardware module includes one or more of:

a processor module;

a storage module;

a networking module;

a security module;

a switch module;

a micro-server module;

a PCIe module;

a graphics module;

or

a general purpose I/O card.

8. The architecture of claim 1, further including one or more of:

a chassis including the surface defining the slot, wherein the chassis includes a standard size corresponding to a rack specification;

a form factor specific off the shelf module;

a form factor specific user defined module.

9. The architecture of claim 1, further including a backboard including one or more of:

a dynamic function backboard;

or

a fixed function backboard.

10. A method comprising:

utilizing a peripheral component interconnect express (PCIe) link directly coupling a slot defined by a surface with a network fabric, wherein the slot accommodates a hardware module.

11. The method of claim 10, further including one or more of:

utilizing a one rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel input/output (I/O);

utilizing a two rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel I/O;

or

utilizing a four rack unit implementation, wherein at least two slots accommodate a processor module, and wherein an additional PCIe link directly couples each of the at least two slots with a back panel I/O.

12. The method of claim 10, further including one or more of:

utilizing at least two slots that accommodate a respective processor module, wherein the network fabric is utilized when the respective processor modules communicate across a PCIe link directly coupling each of the at least two slots with the network fabric;

or

utilizing at least two slots that accommodate a respective processor module, wherein the network fabric is bypassed when the respective processor modules communicate across an additional PCIe link directly coupling each of the at least two slots with a bridge.

13. The method of claim 10, further including one or more of:

utilizing an additional PCIe link directly coupling a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is bypassed when the processor module and the I/O module communicate across the additional PCIe link;

or

utilizing a dual star PCIe link directly coupling four slots with each other, wherein the network fabric is bypassed when at least two hardware modules communicate across the dual star PCIe link.

14. The method of claim 10, further including one or more of:

utilizing a user specific I/O to provide user defined functionality;

or

utilizing a management element to provide management functionality.

15. The method of claim 10, further including one or more of:

utilizing a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack implementation;

utilizing a form factor specific off the shelf module;

utilizing a form factor specific user defined module;

or

utilizing a backboard including one or more of a dynamic function backboard or a fixed function backboard.

16. At least one computer-readable medium comprising one or more instructions that when executed on a computing device cause the computing device to:

utilize a peripheral component interconnect express (PCIe) link directly coupling a slot defined by a surface with a network fabric, wherein the slot is to accommodate a hardware module.

17. The at least one medium of claim 16, wherein when executed the one or more instructions cause the computing device to:

utilize a one rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel input/output (I/O);

utilize a two rack unit implementation, wherein at least one slot accommodates a processor module, and wherein an additional PCIe link directly couples each of the at least one slot with a back panel I/O;

or

utilize a four rack unit implementation, wherein at least two slots accommodate a processor module, and wherein an additional PCIe link directly couples each of the at least two slots with a back panel I/O.

18. The at least one medium of claim 16, wherein when executed the one or more instructions cause the computing device to:

utilize at least two slots that accommodate a respective processor module, wherein the network fabric is utilized when the respective processor modules communicate across a PCIe link directly coupling each of the at least two slots with the network fabric;

or

utilize at least two slots that accommodate a respective processor module, wherein the network fabric is bypassed when the respective processor modules communicate across an additional PCIe link directly coupling each of the at least two slots with a bridge.

19. The at least one medium of claim 16, wherein when executed the one or more instructions cause the computing device to:

utilize an additional PCIe link directly coupling a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is bypassed when the processor module and the I/O module communicate across the additional PCIe link;

or

utilize a dual star PCIe link directly coupling four slots with each other, wherein the network fabric is bypassed when at least two hardware modules communicate across the dual star PCIe link.

20. The at least one medium of claim 16, wherein when executed the one or more instructions cause the computing device to:

utilize a user specific I/O to provide user defined functionality;

or

utilize a management element to provide management functionality.

21. The at least one medium of claim 16, wherein when executed the one or more instructions cause the computing device to:

utilize a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack specification;

utilize a form factor specific off the shelf module;

utilize a form factor specific user defined module;

or

utilize a backboard including one or more of a dynamic function backboard or a fixed function backboard.

22. An apparatus comprising:

a surface defining a slot to accommodate a hardware module; and

logic to,

utilize a peripheral component interconnect express (PCIe) link directly coupling the slot with a network fabric.

23. The apparatus of claim 22, wherein the logic is to,

utilize at least two slots that accommodate a respective processor module, wherein the network fabric is utilized when the respective processor modules communicate across a PCIe link directly coupling each of the at least two slots with the network fabric, or

utilize at least two slots that accommodate a respective processor module, wherein the network fabric is bypassed when the respective processor modules communicate across an additional PCIe link directly coupling each of the at least two slots with a bridge.

24. The apparatus of claim 22, wherein the logic is to,

utilize an additional PCIe link directly coupling a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is bypassed when the processor module and the I/O module communicate across the additional PCIe link, or

utilize a dual star PCIe link directly coupling four slots with each other, wherein the network fabric is bypassed when at least two hardware modules communicate across the dual star PCIe link.

25. The apparatus of claim 22, wherein the logic is to,

utilize a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack specification,

utilize a form factor specific off the shelf module,

utilize a form factor specific user defined module, or

utilize a backboard including one or more of a dynamic function backboard or a fixed function backboard.